参数资料
型号: MPC7410HX500LE
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360
封装: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件页数: 4/52页
文件大小: 943K
代理商: MPC7410HX500LE
12
MPC7410 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Input leakage current,
Vin = L2OVDD/OVDD
1.8
Iin
—20
A
2, 3,
6, 7
2.5
Iin
—35
3.3
Iin
—70
High-Z (off-state) leakage current,
Vin = L2OVDD/OVDD
1.8
ITSI
—20
A
2, 3,
5, 7
2.5
ITSI
—35
3.3
ITSI
—70
Output high voltage, IOH = –6 mA
1.8
VOH
(L2)OVDD – 0.45
V
8
2.5
VOH
1.7
3.3
VOH
2.4
Output low voltage, IOL = 6 mA
1.8
VOL
—0.45
V
8
2.5
VOL
—0.4
3.3
VOL
—0.4
Capacitance, Vin = 0 V, f = 1 MHz
Cin
6.0
pF
3, 4, 7
Notes:
1. Nominal voltages; see Table 3 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals.
3. Excludes factory test signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OVDD and L2OVDD, or both OVDD and L2OVDD must vary in the same
direction (for example, both OVDD and L2OVDD vary by either +5% or –5%).
6. Measured at max OVDD/L2OVDD.
7. Excludes IEEE 1149.1 boundary scan (JTAG) signals.
8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see VIL/VIH/VOL/VOH/CVIH/CVIL DC limits of
1.8 V mode while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by
the UpdateIR TAP state until a different instruction is loaded into the instruction register by either another UpdateIR
or a Test-Logic-Reset TAP state. If only TSRT is asserted to the part, and then a SAMPLE instruction is executed,
there is no way to control or predict what the DC voltage limits are. If HRESET is asserted before executing a
SAMPLE instruction, the DC voltage limits will be controlled by the BVSEL/L2VSEL settings during HRESET.
Anytime HRESET is not asserted (that is, just asserting TRST), the voltage mode is not known until either EXTEST
or CLAMP is executed, at which time the voltage level will be at the DC limits of 1.8 V.
Table 5. DC Electrical Specifications (continued)
At recommended operating conditions (see Table 3)
Characteristic
Nominal
Bus
Voltage1
Symbol
Min
Max
Unit
Notes
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