参数资料
型号: MPC8309VMADDCA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA489
封装: 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-489
文件页数: 17/81页
文件大小: 484K
代理商: MPC8309VMADDCA
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
24
Freescale Semiconductor
Ethernet and MII Management
The following figure provides the AC test load.
Figure 11. AC Test Load
The following figure shows the MII transmit AC timing diagram.
Figure 12. MII Transmit AC Timing Diagram
8.2.1.2
MII Receive AC Timing Specifications
The following table provides the MII receive AC timing specifications.
Table 21. MII Receive AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—400
ns
RX_CLK clock period 100 Mbps
tMRX
—40—
ns
RX_CLK duty cycle
tMRXH/tMRX
35
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
ns
RX_CLK clock rise VIL(min) to VIH(max)
tMRXR
1.0
4.0
ns
RX_CLK clock fall time VIH(max) to VIL(min)
tMRXF
1.0
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)
going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input
signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general,
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
Output
Z0 = 50
OVDD/2
RL = 50
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER
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