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参数资料
| 型号： | MPC8309VMADDCA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA489 |
| 封装： | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-489 |
| 文件页数： | 2/81页 |
| 文件大小： | 484K |
| 代理商： | MPC8309VMADDCA |
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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
10
Freescale Semiconductor
Electrical Characteristics
2.1.3
Output Driver Characteristics
The following table provides information on the characteristics of the output driver strengths.
2.1.4
Input Capacitance Specification
The following table describes the input capacitance for the SYS_CLK_IN pin in the MPC8309.
2.2
Power Sequencing
The device does not require the core supply voltage (VDD) and IO supply voltages (GVDD and OVDD) to
be applied in any particular order. Note that during power ramp-up, before the power supplies are stable
and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input
and output pins are actively driven and cause contention and excessive current. In order to avoid actively
driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O
voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up. In the case
where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before
the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are
stable, wait for a minimum of 32 clock cycles before negating PORESET.
NOTE
There is no specific power down sequence requirement for the device. I/O
voltage supplies (GVDD and OVDD) do not have any ordering requirements
with respect to one another.
Table 3. Output Drive Capability
Driver Type
Output Impedance
(
)
Supply Voltage (V)
Local bus interface utilities signals
42
OVDD =3.3
PCI Signal
25
DDR2 signal
18
GVDD =1.8
DUART, system control, I2C, SPI, JTAG
42
OVDD =3.3
GPIO signals
42
OVDD =3.3
Table 4. Input Capacitance Specification
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input capacitance for all pins except SYS_CLK_IN and
QE_CLK_IN
CI
68
pF
—
Input capacitance for SYS_CLK_IN and QE_CLK_IN
CICLK_IN
10
—
pF
1
Note:
1. The external clock generator should be able to drive 10 pF.
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