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参数资料
| 型号： | MPC8313VRAGDA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516 |
| 封装： | 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-516 |
| 文件页数： | 34/100页 |
| 文件大小： | 1247K |
| 代理商： | MPC8313VRAGDA |
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
39
High-Speed Serial Interfaces (HSSI)
Figure 23. Receiver of SerDes Reference Clocks
9.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8313E SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
Differential mode
— The input amplitude of the differential clock must be between 400 and 1600 mV differential
peak-to-peak (or between 200 and 800 mV differential peak). In other words, each signal wire
of the differential pair must have a single-ended swing less than 800 mV and greater than
200 mV. This requirement is the same for both external DC-coupled or AC-coupled
connection.
— For external DC-coupled connection, as described in Section 9.2.1, “SerDes Reference Clock
Receiver Characteristics,” the maximum average current requirements sets the requirement for
average voltage (common mode voltage) to be between 100 and 400 mV. Figure 24 shows the
SerDes reference clock input requirement for the DC-coupled connection scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
XCOREVSS. Each signal wire of the differential inputs is allowed to swing below and above
requirement for AC-coupled connection scheme.
Single-ended mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude
(single-ended swing) must be between 400 and 800 mV peak-to-peak (from Vmin to Vmax) with
SD_REF_CLK either left unconnected or tied to ground.
— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 26 shows
the SerDes reference clock input requirement for the single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
AC coupled externally. For the best noise performance, the reference of the clock could be DC
Input
Amp
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8313VRAGDB | 功能描述:微处理器 - MPU PBGA W/O ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8313VRAGDC | 功能描述:微处理器 - MPU 8313 REV2.2 NO ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8313VRGDD | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313VRGDDA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313VRGDDB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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