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| 型号： | MPC8313VRAGDB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516 |
| 封装： | 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-516 |
| 文件页数： | 30/100页 |
| 文件大小： | 1247K |
| 代理商： | MPC8313VRAGDB |
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
35
Ethernet: Three-Speed Ethernet, MII Management
8.5.2
MII Management AC Electrical Specifications
Table 39 provides the MII management AC timing specifications.
Table 38. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage (3.3 V) NVDDA/NVDDB
—
2.97
3.63
V
Output high voltage
VOH
IOH = –1.0 mA
NVDDA or NVDDB = Min
2.10
NVDDA +0.3
or
NVDDB +0.3
V
Output low voltage
VOL
IOL = 1.0 mA
LVDDA or LVDDB = Min
VSS
0.50
V
Input high voltage
VIH
—2.0
—
V
Input low voltage
VIL
——
0.80
V
Input high current
IIH
NVDDA or NVDDB = Max
VIN
1 = 2.1 V
—
40
μA
Input low current
IIL
NVDDA or NVDDB = Max
VIN = 0.5 V
–600
—
μA
Note:
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
Table 39. MII Management AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB is 3.3 V ± 0.3V or 2.5 V ± 5%
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
—2.5
—
MHz
2
MDC period
tMDC
—
400
—
ns
MDC clock pulse width high
tMDCH
32
—
ns
MDC to MDIO delay
tMDKHDX
10
—
170
ns
MDIO to MDC setup time
tMDDVKH
5—
—
ns
MDIO to MDC hold time
tMDDXKH
0—
—
ns
MDC rise time
tMDCR
—
10
ns
MDC fall time
tMDHF
—
10
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt Clock Select] field determines the clock frequency
of the Mgmt Clock EC_MDC.)
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相关代理商/技术参数 |
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| MPC8313VRAGDC | 功能描述:微处理器 - MPU 8313 REV2.2 NO ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8313VRGDD | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313VRGDDA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313VRGDDB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313VRGDF | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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