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| 型号： | MPC8323E-MDS-PB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 74/82页 |
| 文件大小： | 0K |
| 描述： | BOARD MODULE DEV SYSTEM 8323 |
| 标准包装： | 1 |
| 类型： | MPU |
| 适用于相关产品： | MPC8323 |
| 所含物品： | 板 |
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
76
Freescale Semiconductor
System Design Information
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
TJ = TC + (RθJC × PD)
where:
TC = case temperature of the package (°C)
RθJC = junction-to-case thermal resistance (°C/W)
PD = power dissipation (W)
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8323E.
24.1
System Clocking
The MPC8323E includes three PLLs.
The system PLL (AVDD2) generates the system clock from the externally supplied CLKIN input.
The frequency ratio between the system and CLKIN is selected using the system PLL ratio
configuration bits as described in Section 22.4, “System PLL Configuration.”
The e300 core PLL (AVDD3) generates the core clock as a slave to the system clock. The frequency
ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio
configuration bits as described in Section 22.5, “Core PLL Configuration.”
The QUICC Engine PLL (AVDD1) which uses the same reference as the system PLL. The QUICC
Engine block generates or uses external sources for all required serial interface clocks.
24.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The voltage
level at each AVDDn pin should always be equivalent to VDD, and preferably these voltages are derived
directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 44, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
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相关代理商/技术参数 |
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|---|---|
| MPC8323E-RDB | 功能描述:开发板和工具包 - 其他处理器 REFERENCE DESIGN PQII PR RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| MPC8323E-RDB | 制造商:Freescale Semiconductor 功能描述:MPC8323E Integrated Multiservice Gateway |
| MPC8323EVRADDC | 功能描述:微处理器 - MPU 8323 NOPB PBGA W/ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8323EVRADDCA | 制造商:Freescale Semiconductor 功能描述:POWERQUICC, 32 BIT POWER ARCHITECTURE SOC, 266MHZ E300, QE, - Trays 制造商:Freescale Semiconductor 功能描述:IC MPU PWRQUICC 266MHZ 516BGA |
| MPC8323EVRAFDC | 功能描述:微处理器 - MPU 8323 NOPB PBGA W/ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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