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参数资料
| 型号： | MPC8323ZQAFDCA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA516 |
| 封装： | 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516 |
| 文件页数： | 9/82页 |
| 文件大小： | 1134K |
| 代理商： | MPC8323ZQAFDCA |
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
17
DDR1 and DDR2 SDRAM
MDQ/MDM output setup with respect to MDQS
tDDKHDS,
tDDKLDS
ns
5
266 MHz
200 MHz
0.9
1.0
—
MDQ/MDM output hold with respect to MDQS
tDDKHDX,
tDDKLDX
ps
5
266 MHz
200 MHz
1100
1200
—
MDQS preamble start
tDDKHMP
–0.5
× tMCK – 0.6 –0.5 × tMCK +0.6
ns
6
MDQS epilogue end
tDDKHME
–0.6
0.6
ns
6
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD
setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied
cycle.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the
MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for a
description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data
mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with D
n_GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol1
Min
Max
Unit
Notes
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