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参数资料
| 型号： | MPC8343ZQAGDB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620 |
| 封装： | 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620 |
| 文件页数： | 4/79页 |
| 文件大小： | 992K |
| 代理商： | MPC8343ZQAGDB |
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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
12
Freescale Semiconductor
RESET Initialization
4.3
TSEC Gigabit Reference Clock Timing
Table 8 provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8343EA.
CLKIN/PCI_CLK duty cycle
tKHK/tCLKIN
40
—
60
%
3
CLKIN/PCI_CLK jitter
—
±150
ps
4, 5
Notes:
1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
6. Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 KHz modulation rate regardless
of input frequency.
Table 8. EC_GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
Parameter
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
tG125
—125
—
MHz
—
EC_GTX_CLK125 cycle time
tG125
—8
—
ns
—
EC_GTX_CLK rise and fall time
LVDD = 2.5 V
LVDD = 3.3 V
tG125R/tG125F
——
0.75
1.0
ns
1
EC_GTX_CLK125 duty cycle
GMII, TBI
1000Base-T for RGMII, RTBI
tG125H/tG125
45
47
—
55
53
%2
EC_GTX_CLK125 jitter
—
±150
ps
2
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD =3.3 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 8.2.2, “RGMII and RTBI AC Timing Specifications for the duty cycle for 10Base-T and 100Base-T
reference clock.
Table 7. CLKIN AC
Timing Specifications (continued)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8347 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MPC8347A | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MPC8347CVRADDB | 功能描述:微处理器 - MPU 8347 PBGA NO-PB W/O ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8347CVRAGD | 功能描述:IC MPU PWRQUICC II PRO 620-PBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:MPC83xx 标准包装:1 系列:MPC85xx 处理器类型:32-位 MPC85xx PowerQUICC III 特点:- 速度:1.2GHz 电压:1.1V 安装类型:表面贴装 封装/外壳:783-BBGA，FCBGA 供应商设备封装:783-FCPBGA（29x29） 包装:托盘 |
| MPC8347CVRAGDB | 功能描述:微处理器 - MPU 8347 PBGA NOPB RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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