参数资料
型号: MPC8343ZQAGDB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
封装: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620
文件页数: 76/79页
文件大小: 992K
代理商: MPC8343ZQAGDB
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
78
Freescale Semiconductor
Document Revision History
3
11/2006
Updated note in introduction.
In the features list in Section 1, “Overview,” updated DDR data rate to show 266 MHz for PBGA
parts for all silicon revisions.
In Table 57, “Suggested PLL Configurations,” added the following row:
Ref No: 823, SPMF: 1000, Core PLL: 0100011, 400-MHz Device Input Clock Freq: 33, CSB
Freq: 266, and Core Freq: 400.
In Section 23, “Ordering Information,” replicated note from document introduction.
2
8/2006
Changed all references to revision 2.0 silicon to revision 3.0 silicon.
Changed number of general purpose parallel I/O pins to 39 in Section 1, “Overview.”
Changed VIH minimum value in Table 35, “JTAG Interface DC Electrical Characteristics,” to
OVDD –0.3.
In Table 40, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min =
2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
In Table 44, “PCI DC Electrical Characteristics,” changed higl-level input voltage values to min = 2
and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”
1
4/2006
Removed Table 20, “Timing Parameters for DDR2-400.”
Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC
Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
Changed Min and Max values for VIH and VIL in Table 40Table 44,“PCI DC Electrical
Characteristics.”
In Table 58, “MPC8343EA (PBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that
MDICO be tied to GRD using an 18
Ω resistor and MCIC1 be tied to DDR power using an 18 Ω
resistor.’
Table 58, “MPC8343EA (PBGA) Pinout Listing,” in row AVDD3 changed power supply from
“AVDD3” to ‘—.’
0
3/2006
Initial public release.
Table 64. Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
相关PDF资料
PDF描述
MPC8347ECVVAJFB 32-BIT, 533 MHz, MICROPROCESSOR, PBGA672
MPC8347ECVVALDB 32-BIT, 667 MHz, MICROPROCESSOR, PBGA672
MPC8347EVRAGDB 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
MPC8347EZQADFB 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
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相关代理商/技术参数
参数描述
MPC8347 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
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