参数资料
型号: MPC8343ZQAGDB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
封装: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620
文件页数: 58/79页
文件大小: 992K
代理商: MPC8343ZQAGDB
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
61
Clocking
Table 53 provides the operating frequencies for the MPC8343EA PBGA under recommended operating
conditions.
19.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 54 shows the multiplication factor
encodings for the system PLL.
Table 53. Operating Frequencies for PBGA
Parameter1
1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
266 MHz
333 MHz
400 MHz
Unit
e300 core frequency (core_clk)
200–266
200–333
200–400
MHz
Coherent system bus frequency (csb_clk)
100–266
MHz
DDR1 memory bus frequency (MCK)2
2 The DDR data rate is 2× the DDR memory bus frequency.
100–133
MHz
DDR2 memory bus frequency (MCK)3
3 The DDR data rate is 2× the DDR memory bus frequency.
100–133
MHz
Local bus frequency (LCLKn)4
4 The local bus frequency is , , or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBIUCM]).
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66
MHz
Security core maximum internal operating frequency
133
MHz
USB_DR, USB_MPH maximum internal operating
frequency
133
MHz
Table 54. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication Factor
0000
× 16
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111
× 7
1000
× 8
1001
× 9
1010
× 10
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