参数资料
型号: MPC8349E-MITXE
厂商: Freescale Semiconductor
文件页数: 12/48页
文件大小: 0K
描述: BOARD REFERENCE FOR MPC8349
产品培训模块: MPC834x PowerQUICC II Processors
标准包装: 1
系列: PowerQUICC II™ PRO
类型: MPU
适用于相关产品: MPC8349E
所含物品: 模块和其他硬件
相关产品: MPC8349ECZUAJFB-ND - IC MPU POWERQUICC II PRO 672TBGA
MPC8349ECVVAJFB-ND - IC MPU POWERQUICC II PRO 672TBGA
MPC8349CZUAJFB-ND - IC MPU POWERQUICC II PRO 672TBGA
MPC8349CZUAJDB-ND - IC MPU POWERQUICC II PRO 672TBGA
MPC8349CZUAGDB-ND - IC MPU POWERQUICC II PRO 672TBGA
MPC8349CVVAJFB-ND - IC MPU POWERQUICC II PRO 672TBGA
MPC8349CVVAJDB-ND - IC MPU POWERQUICC II PRO 672TBGA
MPC8349CVVAGDB-ND - IC MPU POWERQUICC II 672TBGA
MPC8349ZUAJDB-ND - IC MPU PWRQUICC II 672-TBGA
MPC8349ZUAJFB-ND - IC MPU PWRQUICC II 672-TBGA
更多...
其它名称: MPC8349E-MITXE -ND
MPC8349E-mITXE Board
Table 5. PCF8574A (U10) Bit Descriptions (continued)
PCF8574A
(U10) bit[0..7]
4
Name
MPCI_CLKRUN
Read/Write
Read/Write
Description
MiniPCI clock run signal level, defined by the PCI Mobile Design
Guide.
0: MiniPCI clock is in normal operating frequency
1: MiniPCI clock is stopped or running very low
5
PCI_M66EN
Read only, write
has no effect
PCI M66EN Signal
0: PCI M66EN signal is low, indicates the PCI cards on PCI slot and
miniPCI slot are not 66 MHz capable
1: PCI M66EN signal is high, indicates the PCI cards on PCI slot and
miniPCI slot are 66 MHz capable
6
BOOT0
Read only, write
has no effect
Used to determine which Flash is used for boot Flash
0: Flash 0 (U4) is the boot Flash
1: Flash 1 (U7) is the boot Flash
7
Not used
The DS1339 RTC is connected to I 2 C with address 0x68. The software running on PowerPC core can read
or write to the RTC through the I2C2 interface.
1.2.8
Compact Flash Interface
A compact Flash interface connects directly to the local bus without a PCMCIA controller. The true IDE
mode is the only compact Flash operating mode supported by this connection. Hot insertion and removal
is not supported. The MPC8349E universal programmable machine A (UPMA) is used to generate the
required timing for IORD and IOWR through the LGPL0 and LGPL1 signals.
The true IDE mode requires three address signals (A[0:2]) and two chip-enable signals (CE[1:2]) to
address the 10 registers in the AT task file. Therefore, glue logic is used to split CS3 into two regions. One
chip-select signal (CS3) is assigned to the compact Flash interface. Glue logic is used to generate the CE1
and CE2 signals required by the compact Flash. The logic simply uses the local bus address A22 to
determine which chip-enable signal is generated. See Figure 7 .
CS3
LBA22
CE1
CE2
Figure 7. CE1 and CE2 Generation Logic
MPC8349E-mITXE Reference Design Platform User’s Guide, Rev. 2
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
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