参数资料
型号: MPC8358ECZQAGDGA
厂商: Freescale Semiconductor
文件页数: 81/95页
文件大小: 0K
描述: MPU POWERQUICC II PRO 668-PBGA
标准包装: 36
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
电压: 1.2V
安装类型: 表面贴装
封装/外壳: 668-BBGA 裸露焊盘
供应商设备封装: 668-PBGA-PGE(29x29)
包装: 托盘
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
82
Freescale Semiconductor
Clocking
22.4
Suggested PLL Configurations
To simplify the PLL configurations, the device might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine block PLL. The clock
domains are independent, and each of their PLLs are configured separately. Both of the domains has one
common input clock. Table 74 shows suggested PLL configurations for 33 and 66 MHz input clocks and
illustrates each of the clock domains separately. Any combination of clock domains setting with same
input clock are valid. Refer to Section 22, “Clocking,” for the appropriate operating frequencies for your
device.
Table 74. Suggested PLL Configurations
Conf
No.1
SPMF
CORE
PLL
CEPMF
CEPDF
Input
Clock Freq
(MHz)
CSB Freq
(MHz)
Core Freq
(MHz)
QUICC
Engine
Freq (MHz)
400
(MHz)
533
(MHz)
667
(MHz)
33 MHz CLKIN/PCI_SYNC_IN Options
s1
0100
0000100
33
133
266
∞∞
s2
0100
0000101
33
133
333
∞∞
s3
0101
0000100
33
166
333
∞∞
s4
0101
0000101
33
166
416
∞∞
s5
0110
0000100
33
200
400
∞∞
s6
0110
0000110
33
200
600
s7
0111
0000011
33
233
350
∞∞
s8
0111
0000100
33
233
466
∞∞
s9
0111
0000101
33
233
583
s10
1000
0000011
33
266
400
∞∞
s11
1000
0000100
33
266
533
∞∞
s12
1000
0000101
33
266
667
s13
1001
0000010
33
300
∞∞
s14
1001
0000011
33
300
450
∞∞
s15
1001
0000100
33
300
600
s16
1010
0000010
33
333
∞∞
s17
1010
0000011
33
333
500
∞∞
s18
1010
0000100
33
333
667
c1
01001
0
33
300
∞∞
c2
01100
0
33
400
∞∞
c3
01110
0
33
466
∞∞
c4
01111
0
33
500
∞∞
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