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参数资料
| 型号： | MPC8378CVRALDA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689 |
| 封装： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件页数： | 10/125页 |
| 文件大小： | 894K |
| 代理商： | MPC8378CVRALDA |
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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
107
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
Eqn. 20
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up the csb_clk frequency
to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and
COREPLL fields in the reset configuration word low register (RCWLR) which is loaded at power-on reset or by one of the
hard-coded reset options. See Chapter 4, “Reset, Clocking, and Initialization,” in the MPC8379E Reference Manual for more
information on the clock subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWLR[DDRCM])
Eqn. 21
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (
2) to create the
differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk.
The internal lbiu_clk frequency is determined by the following equation:
lbiu_clk = csb_clk × (1 + RCWLR[LBCM])
Eqn. 22
Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create the external
local bus clock outputs (LCLK[0:2]). The eLBC clock divider ratio is controlled by LCRR[CLKDIV].
Some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. Those units
have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. Table 69
specifies which units have a configurable clock frequency.
This table provides the operating frequencies for the TePBGA II package under recommended operating conditions (see
Table 3).
Table 69. Configurable Clock Units
Unit
Default Frequency
Options
eTSEC1, eTSEC2
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
eSDHC and I2C11
1 This only applies to I2C1 (I2C2 clock is not configurable).
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Security block
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
USB DR
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
PCI and DMA complex
csb_clk
Off, csb_clk
PCI Express1, 2
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Table 70. Operating Frequencies for TePBGA II
Parameter1
Minimum Operating
Frequency (MHz)
Maximum Operating
Frequency (MHz)
e300 core frequency (core_clk)333
800
Coherent system bus frequency (csb_clk)133
400
DDR2 memory bus frequency (MCK)1
250
400
DDR1 memory bus frequency (MCK) 2
167
333
Local bus frequency (LCLKn)1
—133
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相关代理商/技术参数 |
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|---|---|
| MPC8378CVRALFA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8378CVRALG | 功能描述:微处理器 - MPU PBGA W/O ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8378CVRALGA | 功能描述:微处理器 - MPU 8378 PBGA XT PbFr No ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8378CVRANDA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8378CVRANFA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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