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参数资料
型号： MPC8378CVRALDA
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封装： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数： 101/125页
文件大小： 894K
代理商： MPC8378CVRALDA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
77
19
SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8378E.
19.1
SPI DC Electrical Characteristics
This table provides the DC electrical characteristics for the device SPI.
19.2
SPI AC Timing Specifications
This table provides the SPI input and output AC timing specifications.
This figure provides the AC test load for the SPI.
Figure 51. SPI AC Test Load
The following two figures represent the AC timing from Table 66. Note that although the specifications generally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Table 65. SPI DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
—
VIH
2.0
OVDD + 0.3
V
Input low voltage
—
VIL
–0.3
0.8
V
Input current
—
IIN
—± 30
A
Output high voltage
IOH = –8.0 mA
VOH
2.4
—
V
Output low voltage
IOL = 8.0 mA
VOL
—0.5
V
Output low voltage
IOL = 3.2 mA
VOL
—0.4
V
Table 66. SPI AC Timing Specifications
Parameter
Symbol1
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
tNIKHOV
0.5
6
ns
SPI outputs—Slave mode (external clock) delay
tNEKHOV
28
ns
SPI inputs—Master mode (internal clock) input setup time
tNIIVKH
4—
ns
SPI inputs—Master mode (internal clock) input hold time
tNIIXKH
0—
ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4—
ns
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2—
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the internal
timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin. The maximum SPICLK input frequency is 66.666 MHz.
Output
Z0 = 50
OVDD/2
RL = 50
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