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参数资料
| 型号： | MPC8378CVRALDA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689 |
| 封装： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件页数： | 106/125页 |
| 文件大小： | 894K |
| 代理商： | MPC8378CVRALDA |
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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
81
with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to
16 mA (0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with
the common mode voltage at 400 mV.
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50
to SGND_SRDSn
(xcorevss) DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.
The input amplitude requirement
— This requirement is described in detail in the following sections.
Figure 55. Receiver of SerDes Reference Clocks
20.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the device SerDes reference clock inputs is different depending on the signaling mode used to
connect the clock driver chip and SerDes reference clock inputs as described below.
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
—For external DC-coupled connection, as described in Section 20.2.1, “SerDes Reference Clock Receiver
Characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) to be between 100 mV and 400 mV. Figure 56 shows the SerDes reference clock input requirement
for DC-coupled connection scheme.
—For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since
the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has
its common mode voltage set to SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing
below and above the command mode voltage (SGND_SRDSn). Figure 57 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
Single-ended Mode
— The reference clock can also be single-ended. The SD _REF_CLK input amplitude (single-ended swing) must be
between 400 mV and 800 mVp-p (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to
ground.
—The SDn_REF_CLK input average voltage must be between 200 mV and 400 mV. Figure 58 shows the SerDes
reference clock input requirement for single-ended signaling mode.
Input
Amp
50
50
SDn_REF_CLK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8378CVRALFA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8378CVRALG | 功能描述:微处理器 - MPU PBGA W/O ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8378CVRALGA | 功能描述:微处理器 - MPU 8378 PBGA XT PbFr No ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8378CVRANDA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8378CVRANFA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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