参数资料
型号: MPC8378CVRANDA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封装: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数: 77/125页
文件大小: 894K
代理商: MPC8378CVRANDA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
55
11.3.1
High-Speed Output Path (Write)
This figure provides the data and command output timing diagram.
Figure 34. High Speed Output Path
11.3.1.1
High-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on
the PCB.
Zero clock delay:
tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL
Eqn. 10
With clock delay:
tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL + tCLK_DELAY
Eqn. 11
tDATA_DELAY tCLK_DELAY < tSHSCKL tISU tSHSKHOV
Eqn. 12
This means that data delay should be equal or less than the clock delay in the ideal case where tSHSCLKL =10ns:
tDATA_DELAY tCLK_DELAY < 10 6 4
tDATA_DELAY tCLK_DELAY < 0
11.3.1.2
High-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on
the PCB.
tCLK_DELAY < tSHSCKL + tSHSKHOX + tDATA_DELAY tIH
Eqn. 13
tCLK_DELAY tDATA_DELAY < tSHSCKL + tSHSKHOX tIH
Eqn. 14
This means that clock can be delayed versus data up to 8 ns (external delay line) in ideal case of tSHSCLKL =10ns:
Output Valid Time: tSHSKHOV
Output Hold Time: tSHSKHOX
tIH (2 ns)
tCLK_DELAY
Input at the
SD CLK at
Driving
Edge
Sampling
Edge
the Card Pin
SD Card Pins
tISU (6 ns)
tDATA_DELAY
tSHSCKL
tSHSCK (Clock Cycle)
SD CLK at the
MPC8378E Pin
Output from the
MPC8378E Pins
相关PDF资料
PDF描述
MPC8378EVRAGFA 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
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相关代理商/技术参数
参数描述
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