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参数资料
型号： MPC8378CVRANDA
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封装： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数： 84/125页
文件大小： 894K
代理商： MPC8378CVRANDA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
61
13
I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8378E.
13.1
I2C DC Electrical Characteristics
This table provides the DC electrical characteristics for the I2C interface of the MPC8378E.
13.2
I2C AC Electrical Specifications
The following table provides the AC timing parameters for the I2C interface of the device.
Table 51. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 165 mV.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7
OV
DD
OVDD + 0.3
V
—
Input low voltage level
VIL
–0.3
0.3
OV
DD
V—
Low level output voltage
VOL
00.2
OV
DD
V
1
Output fall time from VIH(min) to VIL(max) with a bus capacitance
from 10 to 400 pF
tI2KLKV
20 + 0.1
C
B
250
ns
2
Pulse width of spikes which must be suppressed by the input filter
tI2KHKL
050
ns
3
Capacitance for each I/O pin
CI
—10
pF
—
Input current
(0 V
V
IN OVDD)
IIN
—± 30
A
4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8379E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter
used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 52. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 51).
Parameter
Symbol1
Min
Max
Unit
Note
SCL clock frequency
fI2C
0400
kHz
—
Low period of the SCL clock
tI2CL
1.3
—
s—
High period of the SCL clock
tI2CH
0.6
—
s—
Setup time for a repeated START condition
tI2SVKH
0.6
—
s—
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
tI2SXKL
0.6
—
s—
Data setup time
tI2DVKH
100
—
ns
—
Data hold time
CBUS compatible masters
I2C bus devices
tI2DXKL
—
0
—
0.9
s
2, 3
Setup time for STOP condition
tI2PVKH
0.6
—
s—
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