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型号： MPC8378E-MDS-PB
厂商： Freescale Semiconductor
文件页数： 38/128页
文件大小： 0K
描述： BOARD PROCESSOR FOR MDS S
标准包装： 1
类型： MPU
适用于相关产品： MPC8378
所含物品： 板
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
17
Table 14 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
This table provides the recommended operating conditions for the DDR SDRAM component(s) when
GVDD(typ) = 2.5 V.
Output low current (VOUT =0.3 V)
IOL
13.4
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
≤ VOUT ≤ GVDD.
5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
Table 14. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS, DQS
CIO
68
pF
1
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 15. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V
Parameter
Symbol
Min
Max
Unit
Note
I/O supply voltage
GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
0.49
× GVDD
0.51
× GVDD
V2, 5
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.18
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.18
V
—
Output leakage current
IOZ
–50
50
μA4
Output high current (VOUT = 1.9 V)
IOH
–15.2
—
mA
—
Output low current (VOUT = 0.38 V)
IOL
15.2
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
≤ V
OUT ≤ GVDD.
5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)
Parameter
Symbol
Min
Max
Unit
Note
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