参数资料
型号: MPC8535EAVTAQGA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783
封装: 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件页数: 115/126页
文件大小: 2861K
代理商: MPC8535EAVTAQGA
PCI
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
89
Figure 54 provides the AC test load for PCI.
Figure 54. PCI AC Test Load
Figure 55 shows the PCI input AC timing conditions.
Figure 55. PCI Input AC Timing Measurement Conditions
HRESET high to first FRAME assertion
tPCRHFV
10
clocks
8
Rise time (20%–80%)
tPCICLK
0.6
2.1
ns
Failing time (20%–80%)
tPCICLK
0.6
2.1
ns
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional
block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
relative to the SYSCLK clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes
PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid
(V) state.
2. See the timing measurement conditions in the
PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OVDD of the signal in
question for 3.3-V PCI signaling levels.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified
frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values
see Section 22, “Clocking.”
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local
Bus Specifications.
9. The reset assertion timing requirement for HRESET is 100
μs.
Table 68. PCI AC Timing Specifications at 66 MHz (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
tPCIVKH
CLK
Input
tPCIXKH
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