参数资料
型号: MPC8535EAVTAQGA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783
封装: 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件页数: 51/126页
文件大小: 2861K
代理商: MPC8535EAVTAQGA
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
RESET Initialization
Freescale Semiconductor
30
2.4.6
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed. The “platform clock (CCB) frequency”
in the following formula refers to the maximum platform (CCB) frequency of the speed bins the part belongs to, which is
defined in Table 73.
For FIFO GMII mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than 167 MHz
For FIFO encoded mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than
167 MHz
2.4.7
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific
section of this document.
2.5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8535E.
Table 10 provides the RESET initialization AC timing specifications for the DDR SDRAM component(s).
Table 11 provides the PLL lock times.
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HREST
100
μs—
Minimum assertion time for SRESET
3—
Sysclk
1
PLL input setup time with stable SYSCLK before HRESET negation
100
μs—
Input setup time for POR configurations (other than PLL config) with respect to negation of
HRESET
4
SYSCLKs
1
Input hold time for all POR configurations (including PLL config) with respect to negation of
HRESET
2
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configurations with respect to
negation of HRESET
5
SYSCLKs
1
HRESET rise time
1
SYSCLK
Notes:
1. SYSCLK is the primary clock input for the MPC8535E.
Table 11. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
100
μs—
Local bus PLL
50
μs—
PCI bus lock time
50
μs—
相关PDF资料
PDF描述
MPC8536EAVTANGA 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783
MC9S08SG32E1WTLR MICROCONTROLLER, PDSO28
MUAC4K64-70TDI SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100
M30623M4-XXXGP 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
M38513M4-XXXFP 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO42
相关代理商/技术参数
参数描述
MPC8535EAVTATH 功能描述:微处理器 - MPU 8535E COMMERCIAL 1250 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8535EAVTATHA 功能描述:微处理器 - MPU 8535 Encrypted RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8535EAVTATLA 功能描述:微处理器 - MPU 8535 ENCRYPTED RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8535EBVTAKG 功能描述:微处理器 - MPU 8535E INDUSTRIAL 600 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8535EBVTAKGA 功能描述:微处理器 - MPU 8535 Encrypted RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324