参数资料
型号: MPC8535ECVTATH
厂商: Freescale Semiconductor
文件页数: 59/126页
文件大小: 0K
描述: MCU PWRQUICC II 1250MHZ 783-PBGA
标准包装: 1
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.25GHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
38
This figure provides the AC test load for the SPI.
Figure 12. SPI AC Test Load
This figure represents the AC timing from Table 21. Note that although the specifications generally reference the rising edge of
the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 13. SPI AC Timing in Master mode (Internal Clock) Diagram
SPI_CS outputs—Master data delay
tNIKHOV2
—6.0
ns
SPI inputs—Master data input setup time
tNIIVKH
5—
ns
SPI inputs—Master data input hold time
tNIIXKH
0—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from
the high state (H) until outputs (O) are valid (V).
3. SPCOM[RxDelay] is set to 0.
4. SPCOM[RxDelay] is set to 1.
Table 21. SPI AC Timing Specifications1 (continued)
Characteristic
Symbol 2
Min
Max
Unit
Note
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
SPICLK (output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
tNIIVKH
tNIKHOX
Output Signals:
SPI_CS[0:3]
(See Note)
tNIKHOV2
tNIKHOX2
Note: The clock edge is selectable on SPI.
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