参数资料
型号: MPC8540CPXAQFC
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 667 MHz, MICROPROCESSOR, PBGA783
封装: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件页数: 64/104页
文件大小: 1353K
代理商: MPC8540CPXAQFC
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
62
Freescale Semiconductor
RapidIO
13.3.2 RapidIO Receiver AC Timing Specifications
The RapidIO receiver AC timing specifications are provided in Table 50. A receiver shall comply with the
specifications for each data rate/frequency for which operation of the receiver is specified. Unless
otherwise specified, these specifications are subject to the following conditions.
The specifications apply over the supply voltage and ambient temperature ranges specified by the
device vendor.
The specifications apply for any combination of data patterns on the data signals.
The specifications apply over the receiver common mode and differential input voltage ranges.
Clock specifications apply only to clock signals.
Data specifications apply only to data signals (FRAME, D[0:7])
Table 50. RapidIO Receiver AC Timing Specifications—500 Mbps Data Rate
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Duty cycle of the clock input
DC
47
53
%
1, 5
Data valid
DV
1080
ps
2
Allowable static skew between any two data inputs
within a 8-/9-bit group
tDPAIR
380
ps
3
Allowable static skew of data inputs to associated clock
tSKEW,PAIR
–300
300
ps
4
Notes:
1.Measured at VID = 0 V.
2.Measured using the RapidIO receive mask shown in Figure 39.
3.See Figure 42.
5.Guaranteed by design.
Table 51. RapidIO Receiver AC Timing Specifications—750 Mbps Data Rate
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Duty cycle of the clock input
DC
47
53
%
1, 5
Data valid
DV
600
ps
2
Allowable static skew between any two data inputs
within a 8-/9-bit group
tDPAIR
—400
ps
3
Allowable static skew of data inputs to associated clock
tSKEW,PAIR
–267
267
ps
4
Notes:
1.Measured at VID = 0 V.
2.Measured using the RapidIO receive mask shown in Figure 39.
5.Guaranteed by design.
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