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参数资料
| 型号： | MPC8544ECVTAQJB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783 |
| 封装： | 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783 |
| 文件页数： | 14/120页 |
| 文件大小： | 1321K |
| 代理商： | MPC8544ECVTAQJB |
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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
110
Freescale Semiconductor
System Design Information
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there should be a 1-F ceramic chip capacitor on each side of the device. This should be
done for all SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-F, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
21.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to VDD, TVDD, BVDD, OVDD, GVDD, and LVDD as
required. All unused active high inputs should be connected to GND. All NC (no connect) signals must
remain unconnected. Power and ground connections must be made to all external VDD, TVDD, BVDD,
OVDD, GVDD, and LVDD, and GND pins of the device.
21.6
Pull-Up and Pull-Down Resistor Requirements
The MPC8544E requires weak pull-up resistors (2–10 k
Ω is recommended) on open drain type pins
including I2C pins and MPIC interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 69. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1] and TEST_SEL pins
must be set to a proper state during POR configuration. Refer to the pinout listing table (Table 62) for more
details. Refer to the PCI 2.2 Local Bus Specifications, for all pullups required for PCI.
21.7
Output Buffer DC Impedance
The MPC8544E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers,
an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is
components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed
(SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the
resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then,
Z0 =(RP +RN)/2.
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