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型号： MPC8547ECVTAQGB
厂商： Freescale Semiconductor
文件页数： 58/151页
文件大小： 0K
描述： MPU POWERQUICC III 783-PBGA
标准包装： 1
系列： MPC85xx
处理器类型： 32-位 MPC85xx PowerQUICC III
速度： 1.0GHz
电压： 1.1V
安装类型： 表面贴装
封装/外壳： 783-BBGA，FCBGA
供应商设备封装： 783-FCPBGA（29x29）
包装： 托盘
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
150
Freescale Semiconductor
Document Revision History
2
04/2008
Removed 1:1 support on Table 82, “e500 Core to CCB Clock Ratio.”
Removed MDM from Table 18, “DDR SDRAM Input AC Timing Specifications.” MDM is an Output.
Figure 57, “PLL Power Supply Filter Circuit with PLAT Pins” (AVDD_PLAT).
Figure 58, “PLL Power Supply Filter Circuit with CORE Pins” (AVDD_CORE).
Split Figure 59, “PLL Power Supply Filter Circuit with PCI/LBIU Pins,” (formerly called just “PLL Power
Supply Filter Circuit”) into three figures: the original (now specific for AVDD_PCI/AVDD_LBIU) and two
new ones.
1
10/2007
Adjusted maximum SYSCLK frequency down in Table 5, “SYSCLK AC Timing Specifications” per
device erratum GEN-13.
Clarified notes to Table 6, “EC_GTX_CLK125 AC Timing Specifications.”
Added Section 4.4, “PCI/PCI-X Reference Clock Timing.”
Clarified descriptions and added PCI/PCI-X to Table 9, “PLL Lock Times.”
Removed support for 266 and 200 Mbps data rates per device erratum GEN-13 in Section 6, “DDR and
DDR2 SDRAM.”
Clarified Note 4 of Table 19, “DDR SDRAM Output AC Timing Specifications.”
Clarified the reference clock used in Section 7.2, “DUART AC Electrical Specifications.”
Corrected VIH(min) in Table 22, “GMII, MII, RMII, and TBI DC Electrical Characteristics.”
Corrected VIL(max) in Table 23, “GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical
Characteristics.”
Removed DC parameters from Table 24, Table 25, Table 26, Table 27, Table 28, Table 29, Table 32,
Table 34, and Table 35.
Corrected VIH(min) in Table 36, “MII Management DC Electrical Characteristics.”
Corrected tMDC(min) in Table 37, “MII Management AC Timing Specifications.”
Updated parameter descriptions for tLBIVKH1, tLBIVKH2, tLBIXKH1, and tLBIXKH2 in Table 40, “Local Bus
Timing Parameters (BVDD = 3.3 V)—PLL Enabled” and Table 40, “Local Bus Timing Parameters
(BVDD = 2.5 V)—PLL Enabled.”
Updated parameter descriptions for tLBIVKH1, tLBIVKL2, tLBIXKH1, and tLBIXKL2 in Table 42, “Local Bus
Timing Parameters—PLL Bypassed.” Note that tLBIVKL2 and tLBIXKL2 were previously labeled tLBIVKH2
and tLBIXKH2.
Added LUPWAIT signal to Figure 23, “Local Bus Signals (PLL Enabled)” and Figure 24, “Local Bus
Signals (PLL Bypass Mode).”
Added LGTA signal to Figure 25, Figure 26, Figure 27 and Figure 28.
Corrected LUPWAIT assertion in Figure 26 and Figure 28.
Clarified the PCI reference clock in Section 15.2, “PCI/PCI-X AC Electrical Specifications”
Added Section 17.1, “Package Parameters.”
Added PBGA thermal information in Section 21.2, “Thermal for Version 2.1.1, 2.1.2, and 2.1.3 Silicon
FC-PBGA with Full Lid and Version 3.1.x Silicon with Stamped Lid.”
Updated.”
Updated Table 87, “Part Numbering Nomenclature.”
0
07/2007
Initial Release
Table 88. Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
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