收藏本站
参数资料
型号： MPC8555CPXAJD
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
封装： 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件页数： 61/88页
文件大小： 772K
代理商： MPC8555CPXAJD
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 3.1
64
Freescale Semiconductor
Package and Pin Listings
CPM
PA[8:31]
J7, J8, K8, K7, K6, K3, K2, K1, L1, L2, L3, L4, L5, L8,
L9, L10, L11, M10, M9, M8, M7, M6, M3, M2
I/0
OVDD
PB[18:31]
P7, P6, P5, P4, P3, P2, P1, R1, R2, R3, R4, R5, R6,
R7
I/0
OVDD
PC[0, 1, 4-29]
R8, R9, T9, T6, T5, T4, T1, U1, U2, U3, U4, U7, U8,
U9, U10, V9, V6, V5, V4, V3, V2, V1, W1, W2, W3,
W6, W7, W8
I/0
OVDD
PD[7, 14-25, 29-31]
Y4, AA2, AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4,
AC3, AC2, AC1, AD6, AE3, AE2
I/0
OVDD
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
2. Recommend a weak pull-up resistor (2–10 k
) be placed on this pin to OVDD.
3. TEST_SEL0 must be pulled-high, TEST_SEL1 must be tied to ground.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8555E is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
pull-down resistor. If an external
device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is intended
to be high during reset.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
pull-up or pull-down
resistors. See Section 15.2, “Platform/System PLL Ratio.”
8. The value of LALE and LGPL2 at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-k
pull-up or
pull-down resistors. See the Section 15.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
10.This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
PCI device. Refer to the
PCI Specification.
11.This output is actively driven during reset rather than being three-stated during reset.
12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13.These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
and regulation.
14.Internal thermally sensitive resistor.
15.No connections should be made to these pins.
16.These pins are not connected for any functional use.
17.PCI specifications recommend that a weak pull-up resistor (2–10 k
) be placed on the higher order pins to OVDD when
using 64-bit buffer mode (pins PCI_AD[63:32] and PCI2_C_BE[7:4]).
19. If this pin is connected to a device that pulls down during reset, an external pull-up is required to that is strong enough to pull
this signal to a logic 1 during reset.
20. Recommend a pull-up resistor (~1 k
) be placed on this pin to OVDD.
21. These are test signals for factory use only and must be pulled up (100
το 1k) to OVDD for normal machine operation.
22. If this signal is used as both an input and an output, a weak pull-up (~
10k) is required on this pin.
23. MSYNC_IN and MSYNC_OUT should be connected together for proper operation.
Table 43. MPC8555E Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
相关PDF资料
PDF描述
MC3S12XEP100J1MALR 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, QFP112
MPC8543PXAQGB 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783
MPC8545EVTAQGA 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783
MPC8547ECPXAUJB 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA783
MC312XDP512F0VFV 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144
相关代理商/技术参数
参数描述
MPC8555CVTAJD 功能描述:微处理器 - MPU PQ 37 LITE 8555 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8555ECPXAJD 功能描述:微处理器 - MPU PQ 37 LITE 8555E RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8555ECPXALF 功能描述:微处理器 - MPU PQ 37 LITE 8555E RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8555ECVTAJD 功能描述:微处理器 - MPU PQ 37 LITE 8555E RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8555ECVTALF 功能描述:微处理器 - MPU PQ 37 LITE 8555E RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*