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| 型号： | MPC8555CPXAJD |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783 |
| 封装： | 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783 |
| 文件页数： | 88/88页 |
| 文件大小： | 772K |
| 代理商： | MPC8555CPXAJD |
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MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 3.1
Freescale Semiconductor
9
Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
2.1.2
Power Sequencing
One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
Table 1. Absolute Maximum Ratings 1
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.32
0.3 to 1.43 (for 1 GHz only)
V
PLL supply voltage
AVDD
–0.3 to 1.32
0.3 to 1.43 (for 1 GHz only)
V
DDR DRAM I/O voltage
GVDD
–0.3 to 3.63
V
Three-speed Ethernet I/O, MII management voltage
LVDD
–0.3 to 3.63
–0.3 to 2.75
V
CPM, PCI, local bus, DUART, system control and power
management, I2C, and JTAG I/O voltage
OVDD
–0.3 to 3.63
V
3
Input voltage
DDR DRAM signals
MVIN
–0.3 to (GVDD + 0.3)
V
2, 5
DDR DRAM reference
MVREF
–0.3 to (GVDD + 0.3)
V
2, 5
Three-speed Ethernet signals
LVIN
–0.3 to (LVDD + 0.3)
V
4, 5
CPM, Local bus, DUART,
SYSCLK, system control and
power management, I2C, and
JTAG signals
OVIN
–0.3 to (OVDD + 0.3)
V
5
PCI
OVIN
–0.3 to (OVDD + 0.3)
V
6
Storage temperature range
TSTG
–55 to 150
°C
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 3.
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