参数资料
型号: MPC8560VTAQFC
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件页数: 20/104页
文件大小: 1244K
代理商: MPC8560VTAQFC
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
22
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
different than the delays seen in simulation, depending on the system topology. If a heavily loaded system
is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM.
7
Ethernet: Three-Speed, MII Management
This section provides the AC and DC electrical characteristics for three-speed and MII management.
7.1
Three-Speed Ethernet Controller (TSEC)
(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical
Characteristics
The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII
(media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent
interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and
MDC (management data clock). The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII,
MII, and TBI interfaces can be operated at 3.3 or 2.5 V. Whether the GMII, MII, or TBI interface is
operated at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The RGMII and RTBI
interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer
Device Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are
7.1.1
TSEC DC Electrical Characteristics
All GMII,MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes
specified in Table 19 and Table 20. The potential applied to the input of a GMII,MII, TBI, RGMII, or RTBI
receiver may exceed the potential of the receiver’s power supply (i.e., a GMII driver powered from a 3.6
V supply driving VOH into a GMII receiver powered from a 2.5 V supply). Tolerance for dissimilar GMII
driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI signals are
based on a 2.5 V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 18. Expected Delays for Address/Command
Load
Delay
Unit
4 devices (12 pF)
3.0
ns
9 devices (27 pF)
3.6
ns
36 devices (108 pF) + 40 pF compensation capacitor
5.0
ns
36 devices (108 pF) + 80 pF compensation capacitor
5.2
ns
Table 19. GMII, MII, and TBI DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Supply voltage 3.3 V
LVDD
3.13
3.47
V
Output high voltage (LVDD = Min, IOH = –4.0 mA)
VOH
2.40
LVDD + 0.3
V
Output low voltage (LVDD = Min, IOL = 4.0 mA)
VOL
GND
0.50
V
Input high voltage
VIH
1.70
LVDD + 0.3
V
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