参数资料
型号: MPC8560VTAQFC
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件页数: 26/104页
文件大小: 1244K
代理商: MPC8560VTAQFC
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
28
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
7.2.3
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
7.2.3.1
TBI Transmit AC Timing Specifications
Table 25 provides the TBI transmit AC timing specifications.
Figure 12 shows the TBI transmit AC timing diagram.
Figure 12. TBI Transmit AC Timing Diagram
Table 25. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
GTX_CLK clock period
tTTX
—8.0
ns
GTX_CLK duty cycle
tTTXH/tTTX
40
60
%
TCG[9:0] setup time GTX_CLK going high
tTTKHDV
2.0
ns
TCG[9:0] hold time from GTX_CLK going high
tTTKHDX
1.0
ns
GTX_CLK clock rise and fall time
tTTXR, tTTXF
2,3
——
1.0
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI
transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid
state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high
(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of
tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
GTX_CLK
TCG[9:0]
tTTX
tTTXH
tTTXR
tTTXF
tTTKHDV
tTTKHDX
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