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参数资料
| 型号： | MPC8572EAMC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 21/72页 |
| 文件大小： | 0K |
| 描述： | MPC8572 AMC RAPID SYSTEM |
| 标准包装： | 1 |
| 系列： | PowerQUICC III™ |
| 类型： | MPU |
| 适用于相关产品： | MPC8572E |
| 所含物品： | 板 |
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Controls and Indicators
Table 4-1. MPC8572EAMC DIP Switch Listing (continued)
Feature
SW500.4
SW500.5
SW500.6
SW500.7
SW500.8
SW501.1
SW501.2
SW501.3
SW501.4
Default Settings
[OFF = 1, ON = 0)
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
ON
Comments
[SW500.4:5] = ON:ON. MPC8572E acts as agent on all interfaces
[SW500.4:5] = OFF:ON. MPC8572E acts as end point on PCIE #1 host
[SW500.4:5] = ON:OFF. MPC8572E acts as end point on SRIO & PCIE #1 host
[SW500.4:5] = OFF:OFF. MPC8572E acts as the host processor 1
[SW500.6:8] = OFF:ON:ON. IO Port Selection = SRIO 100-MHz clock, 2.5 Gbps (x4)
[SW500.6:8] = ON:OFF:ON. IO Port Selection = SRIO/PCIE 100-MHz clock, 2.5 Gbps
[SW500.6:8] = OFF:OFF:ON. IO Port Selection = SRIO/PCIE 100-MHz clock, 1.25/2.5 Gbps (x4)
[SW500.6:8] = OFF:ON:OFF. IO Port Selection = SRIO 100-MHz clock, 1.25 Gbps (x4)
[SW500.6:8] = ON:ON:OFF. IO Port Selection = SRIO 125 MHz, 3.125 Gbps (x4) 1
SW501
[SW501.1] = ON Boot Sequence Configuration = Boot Sequencer Enabled
[SW501.1] = OFF Boot Sequence Configuration = Boot Sequencer Disabled 1
CPU Boot Config:
[SW501.2:3] = ON:ON.CPU boot hold-off both cores
[SW501.2:3] = OFF:ON. E500 Core 0 allowed to boot, Core 1 in boot hold-off 1
[SW501.2:3] = ON:OFF. E500 Core 1 allowed to boot, Core 0 in boot hold-off
[SW501.2:3] = OFF:OFF. Both cores boot without external master
RIO System Size:
[SW501.4] = ON. Large system size, up to 65,536 devices 1
[SW501.4] = OFF. Small system size, up to 256 devices
Note:
1
Default
Check the default positions of the board first and ensure that the board is operational before changing any
settings. Please also ensure that the selected settings are within the maximum supported operating
characteristics of the device.
4.2
Jumpers
There is one jumper on the board as described in Table 4-2 . This jumper is used to include or isolate the
System CPLD from the JTAG chain.
Table 4-2. Jumper Position
Jumper
J12
Description
Selects the Reset and System CPLD JTAG chain.
? Position 1-2: only Reset CPLD is in the chain
? Position 2-3: both Reset and System CPLDs are in the chain.
Note: If the Reset CPLD is blank, then position 1-2 must be used to program it.
MPC8572EAMC Advanced Mezzanine Card User Guide, Rev. 1.2
Freescale Semiconductor
4-3
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| MPC8572EAMC-SA | 制造商:Freescale Semiconductor 功能描述:MPC8572 AMC RAPID SYSTEM - Bulk |
| MPC8572ECLPXARLE | 功能描述:微处理器 - MPU R211 Enc SnPb 1067LP Ext RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8572ECLPXATLD | 功能描述:微处理器 - MPU 1200 ExtTmp LwPwr RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8572ECLPXATLE | 功能描述:微处理器 - MPU R211 Enc SnPb 1200LP Ext RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8572ECLPXAULD | 功能描述:微处理器 - MPU 1333 EXT TEMP RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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