
31-10
MPC866 PowerQUICC Family User’s Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
I2C Parameter RAM
Table 31-6. I2C Parameter RAM Memory Map
Offset 1
1
Name
Width
Description
0x00
RBASE
Hword Rx/TxBD table base address. Indicate where the BD tables begin in the dual-port
RAM. Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs
are allocated for the Tx and Rx sections of the I2C. Initialize RBASE/TBASE before
enabling the I2C. Furthermore, do not congure BD tables of the I2C to overlap any
other active controller’s parameter RAM.
RBASE and TBASE should be divisible by eight.
0x02
TBASE
Hword
0x04
RFCR
Byte
Rx/Tx function code. The value to appear on AT[1–3] when the associated SDMA
channel accesses memory. Also controls the byte-ordering convention for transfers.
0x05
TFCR
Byte
0x06
MRBLR Hword Maximum receive buffer length. Denes the maximum number of bytes the I2C
receiver writes to a receive buffer before moving to the next buffer. The receiver writes
fewer bytes to the buffer than the MRBLR value if an error or end-of-frame occurs.
Receive buffers should not be smaller than MRBLR.
Transmit buffers are unaffected by MRBLR and can vary in length; the number of
bytes to be sent is specied in TxBD[Data Length].
MRBLR is not intended to be changed while the I2C is operating. However it can be
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles
back-to-back). The change takes effect when the CP moves control to the next
RxBD. To guarantee the exact RxBD on which the change occurs, change MRBLR
only while the I2C receiver is disabled. MRBLR should be greater than zero.
0x08
RSTATE
Word Rx internal state. Reserved for CPM use.
0x0C
RPTR
Word Rx internal data pointer 2 is updated by the SDMA channels to show the next address
in the buffer to be accessed.
2
Normally, these parameters need not be accessed.
0x10
RBPTR
Hword RxBD pointer. Points to the next descriptor the receiver transfers data to when it is in
an idle state or to the current descriptor during frame processing for each I2C
channel. After a reset or when the end of the descriptor table is reached, the CP
initializes RBPTR to the value in RBASE. Most applications should not write RBPTR,
but it can be modied when the receiver is disabled or when no receive buffer is used.
0x12
RCOUN
T
Hword Rx internal byte count
2 is a down-count value that is initialized with the MRBLR value
and decremented with every byte the SDMA channels write.
0x14
RTEMP
Word Rx temp. Reserved for CPM use.
0x18
TSTATE
Word Tx internal state. Reserved for CPM use.
0x1C
TPTR
Word Tx internal data pointer
2 is updated by the SDMA channels to show the next address
in the buffer to be accessed.
0x20
TBPTR
Hword TxBD pointer. Points to the next descriptor that the transmitter transfers data from
when it is in an idle state or to the current descriptor during frame transmission. After
a reset or when the end of the descriptor table is reached, the CPM initializes TBPTR
to the value in TBASE.Most applications should not write TBPTR, but it can be
modied when the transmitter is disabled or when no transmit buffer is used.
0x22
TCOUNT Hword Tx internal byte count
2 is a down-count value initialized with TxBD[Data Length] and
decremented with every byte read by the SDMA channels.
0x24
TTEMP
Word Tx temp. Reserved for CP use.
0x28-0x2F
—