
MOTOROLA
Chapter 44. Fast Ethernet Controller (FEC)
44-13
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Programming Model
44.4 Programming Model
The FEC software model is similar to that used by the 10-Mbps Ethernet implemented on
the CPM. To support higher data rates, the FEC has a different internal architecture, which
changes the programming model slightly. However, efforts have been taken to minimize the
differences required by the interrupt handlers. The FEC’s registers are very different from
those of the CPM-based internal Ethernet controller.
PD[6]
RTS4
MII_RX_DV
V16
General-purpose I/O port D bit 6—This is bit 6 of the general-purpose I/O port D.
RTS4—Active low request to send output indicates that SCC4 is ready to transmit data.
MII receive data valid—When input signal RX_DV is asserted, the PHY is indicating that a
valid nibble is present on the MII. This signal shall remain asserted from the rst recovered
nibble of the frame through the last nibble. Assertion of RX_DV must start no later than the
SFD and exclude any EOF.
PD[5]
REJECT2
MII_TXD[3]
U15
General-purpose I/O port D bit 5—This is bit 5 of the general-purpose I/O port D.
Reject 2—This input to SCC2 allows a CAM to reject the current Ethernet frame after it
determines the frame address did not match.
MII transmit data 3—Output signal TXD[3] represents bit 3 of the nibble of data when
TX_EN is asserted and has no meaning when TX_EN is negated.
PD[4]
REJECT3
MII_TXD[2]
U16
General-purpose I/O port D bit 4—This is bit 4 of the general-purpose I/O port D.
Reject 3—This input to SCC3 allows a CAM to reject the current Ethernet frame after it
determines the frame address did not match.
MII transmit data 2—Output signal TXD[2] represents bit 2 of the nibble of data when
TX_EN is asserted and has no meaning when TX_EN is negated.
PD[3]
REJECT4
MII_TXD[1]
W16
General-purpose I/O port D bit 3—This is bit 3 of the general-purpose I/O port D.
Reject 4—This input to SCC4 allows a CAM to reject the current Ethernet frame after it
determines the frame address did not match.
MII transmit data 1—Output signal TXD[1] represents bit 1 of the nibble of data when
TX_EN is asserted and has no meaning when TX_EN is negated.
MII_TX_EN
V15
MII transmit enable—Output signal TX_EN indicates when there are valid nibbles being
presented on the MII. This signal is asserted with the rst nibble of preamble and is negated
prior to the rst TX_CLK following the nal nibble of the frame. This signal resets to
three-state with a weak internal pull-down to ensure compatibility with 8xx applications that
may have tied SPARE3 (V15) to VCC or GND. This pin will be 3-V only and must not be
pulled up to +5 V.
MII_CRS
B7
MII carrier receive sense—When input signal CRS is asserted the transmit or receive
medium is not idle. In the event of a collision, CRS will remain asserted through the duration
of the collision.
MII_COL
H4
MII collision—Input signal COL is asserted upon detection of a collision, and will remain
asserted while the collision persists. The behavior of this signal is not specied for
full-duplex mode.
MII_MDIO
H18
MII management data—Bidirectional signal, MDIO transfers control information between
the PHY and MAC. Transitions synchronously to MDC.
Table 44-6. FEC Signal Descriptions (continued)
Name
Pin
Number
Description