参数资料
型号: MPC866TVR100A
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PBGA357
封装: LEAD FREE, PLASTIC, BGA-357
文件页数: 7/96页
文件大小: 1303K
代理商: MPC866TVR100A
MPC866/MPC859 Hardware Specifications, Rev. 2
Freescale Semiconductor
15
Power Supply and Power Sequencing
8
Power Supply and Power Sequencing
This section provides design considerations for the MPC866/859 power supply. The MPC866/859 has a core voltage
(VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage VDDH. The I/O section
of the MPC866/859 is supplied with 3.3 V across VDDH and VSS (GND).
Signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, and MII_MDIO
are 5-V tolerant. All inputs cannot be more than 2.5 V greater than VDDH. In addition, 5-V tolerant pins cannot
exceed 5.5 V and the remaining input pins cannot exceed 3.465 V. This restriction applies to power up/down and
normal operation.
One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at
different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the
manner in which different voltages are derived. The following restrictions apply:
VDDL must not exceed VDDH during power up and power down.
VDDL must not exceed 1.9 V and VDDH must not exceed 3.465 V.
These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic discharge
(ESD) protection diodes are forward-biased and excessive current can flow through these diodes. If the system
power supply design does not control the voltage sequencing, the circuit shown in Figure 4 can be added to meet
these requirements. The MUR420 Schottky diodes control the maximum potential difference between the external
bus and core power supplies on powerup and the 1N5820 diodes regulate the maximum potential difference on
powerdown.
Figure 4. Example Voltage Sequencing Circuit
9
Layout Practices
Each VDD pin on the MPC866/859 should be provided with a low-impedance path to the board’s supply.
Furthermore, each GND pin should be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VDD power supply should be bypassed to ground using at least four 0.1 F
bypass capacitors located as close as possible to the four sides of the package. Each board designed should be
characterized and additional appropriate decoupling capacitors should be used if required. The capacitor leads and
associated printed-circuit traces connecting to chip VDD and GND should be kept to less than 1/2” per capacitor lead.
At a minimum, a four-layer board employing two inner layers as VDD and GND planes should be used.
All output pins on the MPC866/859 have fast rise and fall times. Printed-circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.
VDDH
VDDL
1N5820
MUR420
相关PDF资料
PDF描述
MPC866PCVR100A 32-BIT, 100 MHz, RISC PROCESSOR, PBGA357
MPC859DSLVR66A 32-BIT, 66 MHz, RISC PROCESSOR, PBGA357
MPC866TCZP100A 32-BIT, 100 MHz, RISC PROCESSOR, PBGA357
MPC859PZP133A 32-BIT, 133 MHz, RISC PROCESSOR, PBGA357
MPC866TZP100A 32-BIT, 100 MHz, RISC PROCESSOR, PBGA357
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