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参数资料
| 型号： | MPC9229DT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 6/10页 |
| 文件大小： | 359K |
| 代理商： | MPC9229DT |
MPC9229
384
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
PROGRAMMING INTERFACE
Programming the MPC9229
Programming the MPC9229 amounts to properly configuring
the internal PLL dividers to produce the desired synthesized
frequency at the output. The output frequency can be
represented by this formula:
fOUT = (fXTAL ÷ 16) (4 M) ÷ (4 N) or
(1)
fOUT = (fXTAL ÷ 16) M ÷ N(2)
where fXTAL is the crystal frequency, M is the PLL
feedback-divider and N is the PLL post-divider. The input
frequency and the selection of the feedback divider M is limited
by the VCO-frequency range. fXTAL and M must be configured
to match the VCO frequency range of 800 to 1600 MHz in order
to achieve stable PLL operation:
MMIN =4 fVCO,MIN ÷ fXTAL and
(3)
MMAX =4 fVCO,MAX ÷ fXTAL
(4)
For instance, the use of a 16 MHz input frequency requires
the configuration of the PLL feedback divider between M = 200
and M = 400. Table 7 shows the usable VCO frequency and M
divider range for other example input frequencies. Assuming
that a 16 MHz input frequency is used, equation (2) reduces to:
fOUT = M ÷ N
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)1
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fXTAL
Crystal interface frequency range
10
20
MHz
fVCO
VCO frequency range2
2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL M ÷ 4.
800
1600
MHz
fMAX
Output Frequency
N = 00 (
÷ 1)
N = 01 (
÷ 2)
N = 10 (
÷ 4)
N = 11 (
÷ 8)
200
100
50
25
400
200
100
50
MHz
DC
Output duty cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.05
0.3
ns
20% to 80%
fS_CLOCK Serial interface programming clock frequency3
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as
test clock in test mode 6. Refer to APPLICATIONS INFORMATION for more details.
0
10
MHz
tP,MIN
Minimum pulse width
(S_LOAD, P_LOAD)
50
ns
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
ns
tS
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
ns
tJIT(CC)
Cycle-to-cycle jitter
N = 00 (
÷ 1)
N = 01 (
÷ 2)
N = 10 (
÷ 4)
N = 11 (
÷ 8)
90
130
160
190
ps
tJIT(PER)
Period Jitter
N = 00 (
÷ 1)
N = 01 (
÷ 2)
N = 10 (
÷ 4)
N = 11 (
÷ 8)
70
120
140
170
ps
tLOCK
Maximum PLL Lock Time
10
ms
Table 7. MPC9229 Frequency Operating Range
M
M[8:0]
VCO frequency for a crystal interface frequency of
Output frequency for fXTAL = 16 MHz and for N =
10
12
14
16
18
20
1
2
4
16
160
010100000
800
170
010101010
850
180
010110100
810
900
MPC9229
400 MHz Low Voltage PECL Clock Synthesizer
NETCOM
IDT 400 MHz Low Voltage PECL Clock Synthesizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9229
5
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