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参数资料
| 型号： | MPC92439FAR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 900 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 16/16页 |
| 文件大小： | 288K |
| 代理商： | MPC92439FAR2 |
Advanced Clock Drivers Devices
Freescale Semiconductor
9
MPC92439
illustrates a typical power supply filter scheme. The
MPC92439 is most susceptible to noise with spectral content
in the 1 kHz to 1 MHz range. Therefore, the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop that
will be seen between the VCC supply and the MPC92439 pin
of the MPC92439. From the data sheet, the VCC_PLL current
(the current sourced through the VCC_PLL pin) is maximum
20 mA, assuming that a minimum of 2.835 V must be
maintained on the VCC_PLL pin. The resistor shown in
Figure 7 must have a resistance of 10–15
to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20 kHz. As the noise
frequency crosses the series resonant point of an individual
capacitor its overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL. Generally, the resistor/capacitor filter
will be cheaper, easier to implement and provide an adequate
level of supply filtering. A higher level of attenuation can be
achieved by replacing the resistor with an appropriate valued
inductor. A 1000
H choke will show a significant impedance
at 10 kHz frequencies and above. Because of the current
draw and the voltage that must be maintained on the VCC_PLL
pin, a low DC resistance inductor is required (less than 15
).
Figure 7. VCC_PLL Power Supply Filter
Layout Recommendations
The MPC92439 provides sub-nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. Figure 8 shows a representative board layout for the
MPC92439. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 8 is the low impedance connections
between VCC and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors with
good PCB layout techniques will produce effective capacitor
resonances at frequencies adequate to supply the
instantaneous switching current for the MPC92439 outputs. It
is imperative that low inductance chip capacitors are used; it
is equally important that the board layout does not introduce
back all of the inductance saved by using the leadless
capacitors. Thin interconnect traces between the capacitor
and the power plane should be avoided and multiple large
vias should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors. Note the dotted lines
circling the crystal oscillator connection to the device. The
oscillator is a series resonant circuit and the voltage
amplitude across the crystal is relatively small. It is imperative
that no actively switching signals cross under the crystal as
crosstalk energy coupled to these lines could significantly
impact the jitter of the device. Special attention should be
paid to the layout of the crystal to ensure a stable, jitter free
interface between the crystal and the on-board oscillator.
Although the MPC92439 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL), there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.
Figure 8. PCB Board Layout Recommendation
for the PLCC28 Package
The On-Chip Crystal Oscillator
The MPC92439 features an integrated on-chip crystal
oscillator to minimize system implementation cost. The
integrated oscillator is a Pierce-type that uses the crystal in
its parallel resonance mode. It is recommended to use a
10 to 20 MHz crystal with a load specification of CL =10pF.
Crystals with a load specification of CL = 20 pF may be used
at the expense of an slightly higher frequency than specified
for the crystal. Externally connected capacitors on both the
XTAL_IN and XTAL_OUT pins are not required but can be
used to fine-tune the crystal frequency as desired.
The crystal, the trace and optional capacitors should be
placed on the board as close as possible to the MPC92439
XTAL_IN and XTAL_OUT pins to reduce crosstalk of active
signals into the oscillator. Short and wide traces further
reduce parasitic inductance and resistance. It is further
recommended to guard the crystal circuit by placing a ground
ring around the traces and oscillator components. See
Table 12 for recommended crystal specifications.
VCC_PLL
VCC
MPC92439
C1, C2 = 0.01...0.1 F
VCC
CF = 22 F
RF = 10-15
C2
C1
1
C2
CF
XTAL
C1
= VCC
= GND
= Via
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相关代理商/技术参数 |
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| MPC92439KLF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
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| MPC92469AC | 功能描述:时钟合成器/抖动清除器 LVPECL Clock Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MPC92469ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
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