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| 型号： | MPC9315FA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 |
| 文件页数： | 14/16页 |
| 文件大小： | 401K |
| 代理商： | MPC9315FA |
Advanced Clock Drivers Devices
Freescale Semiconductor
7
MPC9315
APPLICATIONS INFORMATION
Programming the MPC9315
The PLL of the MPC9315 supports output clock
frequencies from 18.75 to 160 MHz. Different feedback and
output divider configurations can be used to achieve the
desired input to output frequency relationship. The feedback
frequency and divider should be used to situate the VCO in
the frequency range between 75 and 160 MHz for stable and
optimal operation. The FSELA, FSELB, FSELC pins select
the desired output clock frequencies. Possible frequency
ratios of the reference clock input to the outputs are 1:1, 1:2,
illustrate the various output configurations and frequency
ratios supported by the MPC9315. PSELA controls the output
phase of the QA0 and QA1 outputs, allowing the user to
generate inverted clock signals synchronous to non-inverted
clock signals. See also Example Configurations for the
MPC9315 for further reference.
Table 9. Output Frequency Relationship for QA0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
CLK
÷ 2
0
1
CLK
÷ 4
0
1
0
CLK
÷ 2
CLK
÷ 2
0
1
CLK
÷ 2
CLK
÷ 4
1
0
CLK
2 * CLK
CLK
1
0
1
CLK
2 * CLK
CLK
÷ 2
1
0
CLK
1
CLK
÷ 2
Table 10. Output Frequency Relationship for QB0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
CLK
÷ 2
0
1
CLK
÷ 4
0
1
0
2 * CLK
CLK
0
1
2 * CLK
CLK
÷ 2
1
0
CLK
÷ 2
CLK
÷ 2
1
0
1
CLK
÷ 2
CLK
÷ 4
1
0
CLK
1
CLK
÷ 2
Table 11. Output Frequency Relationship for QC0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
2 * CLK
CLK
0
1
4 * CLK
CLK
0
1
0
2 * CLK
CLK
0
1
4 * CLK
2 * CLK
CLK
1
0
CLK
2 * CLK
CLK
1
0
1
2 * CLK
4 * CLK
CLK
1
0
CLK
1
2 * CLK
CLK
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