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参数资料
| 型号： | MPC9315FA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 |
| 文件页数： | 4/16页 |
| 文件大小： | 401K |
| 代理商： | MPC9315FA |
Advanced Clock Drivers Devices
12
Freescale Semiconductor
MPC9315
Figure 15. Propagation delay (t(), SPO) Test Reference
Figure 16. Output Duty Cycle (DC)
Figure 17. Output-to-Output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
tSK(O)
VCC
GND
tP
T0
DC = tP/T0 x 100%
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
t()
CLK0, 1
FB0, 1
VCC ÷ 2
Figure 18. Cycle-to-Cycle Jitter
Figure 19. Period Jitter
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
TN
TN+1
TJIT(PER) = |TN–1/f0|
T0
tF
tR
VCC=3.3 V
VCC=2.5 V
2.4
1.8 V
0.55
0.6 V
Figure 20. I/O Jitter
Figure 21. Output Transition Time Test Reference
TJIT() = |T0–T1mean|
TCLK0, 1
FB0, 1
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles
TJIT(CC) = |TN–TN+1|
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