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参数资料
| 型号： | MPC932FAR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | MPC900 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | PLASTIC, TQFP-32 |
| 文件页数： | 4/6页 |
| 文件大小： | 126K |
| 代理商： | MPC932FAR2 |
MPC932
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
75
MPC932 AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
fref
Input Reference Frequency
Note 6.
MHz
tos
Output-to-Output Skew
250
600
ps
Note 4.
fVCO
VCO Lock Range
200
480
MHz
fmax
Maximum Output Frequency
(
÷4)
(
÷5)
(
÷6)
120
96
80
MHz
tpd
Reference to EXT_FB Average Delay
TCLK
PECL_CLK
–200
0
200
ps
fref = 50MHz; Note 7.
tpw
Output Duty Cycle (Note 4.)
tCYCLE/2
–750
tCYCLE/2
±500
tCYCLE/2
+750
ps
tr, tf
Output Rise/Fall Time (Note 4.)
0.1
1.0
ns
0.8 to 2.0V
tPLZ, tPHZ
Output Disable Time
2.0
8.0
ns
50
to VCC/2
tPZL
Output Enable Time
2.0
10
ns
50
to VCC/2
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
±100
ps
Note 5.
tlock
Maximum PLL Lock Time
10
ms
4. Measured with 50
to VCC/2 termination.
5. See Applications Info section for more jitter information.
6. Input reference frequency is bounded by VCO lock range and feedback divide selection.
7. tpd measurement uses the averaging feature of the oscilloscope to remove the jitter component.
APPLICATIONS INFORMATION
MPC932
Figure 2. MPC932 Potential Configurations
(Mode = 1)
FBSEL0
`0'
FBSEL1
`0'
FB_In
66MHz
Qn
66MHz
QFB
6
1
Input Ref
66MHz
MPC932
FBSEL0
`1'
FBSEL1
`0'
FB_In
83MHz
Qn
66MHz
QFB
6
1
Input Ref
66MHz
MPC932
FBSEL0
`1'
FBSEL1
`0'
FB_In
75MHz
Qn
60MHz
QFB
6
1
Input Ref
60MHz
MPC932
FBSEL0
`0'
FBSEL1
`1'
FB_In
100MHz
Qn
66MHz
QFB
6
1
Input Ref
66MHz
2
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