Advanced Clock Drivers Devices
Freescale Semiconductor
7
MPC9330
Table 8. MPC9330 Example Configurations (Internal Feedback: FB_SEL = 0)
fref(1) [MHz]
1. fref is the input clock reference frequency (CCLK or XTAL).
PWR_DN
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
12.5–30.0
0
fref
4
(50-120 MHz) fref
4
(50-120 MHz) fref
2
(25-60 MHz)
0
1
fref
4
(50-120 MHz) fref
4
(50-120 MHz) fref
4 ÷ 3
(16.6-40 MHz)
0
1
0
fref
4
(50-120 MHz) fref
2
(25-60 MHz) fref
2
(25-60 MHz)
0
1
fref
4
(50-120 MHz) fref
2
(25-60 MHz) fref
4 ÷ 3
(16.6-40 MHz)
0
1
0
fref
2
(25-60 MHz) fref
4
(50-120 MHz) fref
2
(25-60 MHz)
0
1
0
1
fref
2
(25-60 MHz) fref
4
(50-120 MHz) fref
4 ÷ 3
(16.6-40 MHz)
0
1
0
fref
2
(25-60 MHz) fref
2
(25-60 MHz) fref
2
(25-60 MHz)
0
1
fref
2
(25-60 MHz) fref
2
(25-60 MHz) fref
4 ÷ 3
(16.6-40 MHz)
1
0
fref
2
(25-60 MHz) fref
2
(25-60 MHz) fref
(12.5-30 MHz)
1
0
1
fref
2
(25-60 MHz) fref
2
(25-60 MHz) fref
2 ÷ 3
(8.33-20 MHz)
1
0
1
0
fref
2
(25-60 MHz) fref
(12.5-30 MHz) fref
(12.5-30 MHz)
1
0
1
fref
2
(25-60 MHz) fref
(12.5-30 MHz) fref
2 ÷ 3
(8.33-20 MHz)
1
0
fref
(12.5-30 MHz) fref
2
(25-60 MHz) fref
(12.5-30 MHz)
1
0
1
fref
(12.5-30 MHz) fref
2
(25-60 MHz) fref
2 ÷ 3
(8.33-20 MHz)
1
0
fref
(12.5-30 MHz) fref
(12.5-30 MHz)
1
fref
(12.5-30 MHz) fref
2 ÷ 3
(8.33-20 MHz)
Table 9. MPC9330 Example Configurations (External Feedback and PWR_DN = 0)
PLL
Feedback
fref(1)
[MHz]
1. fref is the input clock reference frequency (CCLK or XTAL).
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 4(2)
2. QAx connected to FB_IN and FSELA=0, PWR_DN=0.
50–120
0
fref
(50-120 MHz) fref
÷ 2
(25-60 MHz)
0
1
fref
(50-120 MHz) fref
÷ 3
(16.6-40 MHz)
0
1
0
fref
(50-120 MHz) fref
÷ 2
(25-60 MHz) fref
÷ 2
(25-60 MHz)
0
1
fref
(50-120 MHz) fref
÷ 2
(25-60 MHz) fref
÷ 3
(16.6-40 MHz)
VCO
÷ 8(3)
3. QAx connected to FB_IN and FSELA=1, PWR_DN=0.
25–60
1
0
fref
(25-60 MHz) fref
2
(50-120 MHz) fref
(25-60 MHz)
1
0
1
fref
(25-60 MHz) fref
2
(50-120 MHz) fref 2
÷ 3
(16.6-40 MHz)
1
0
fref
(25-60 MHz) fref
(25-60 MHz)
1
fref
(25-60 MHz) fref
(25-60 MHz) fref 2
÷ 3
(16.6-40 MHz)
VCO
÷ 12(4)
4. QCx connected to FB_IN and FSELC=1, PWR_DN=0.
16.67–40
0
1
fref
3
(50-120 MHz) fref
3
(50-120 MHz) fref
(16.6-40 MHz)
01
1
fref
3
(50-120 MHz) fref
3 ÷ 2 (25-60 MHz) fref
(16.6-40 MHz)
10
1
fref
3 ÷ 2 (25-60 MHz) fref 3
(50-120 MHz) fref
(16.6-40 MHz)
11
1
fref
3 ÷ 2 (25-60 MHz) fref 3 ÷ 2 (25-60 MHz) fref
(16.6-40 MHz)
Table 10. MPC9330 Example Configurations (External Feedback and PWR_DN = 1)
PLL
Feedback
fref(1)
[MHz]
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 16(2)
12.5–30
1
0
fref
(12.5-30 MHz)
fref 2
(25-60 MHz)
fref
(12.5-30 MHz)
1
0
1
fref
(12.5-30 MHz)
fref 2
(25-60 MHz)
fref 2
÷ 3
(8.33-20 MHz)
1
0
fref
(12.5-30 MHz)
fref
(12.5-30 MHz)
fref
(12.5-30 MHz)
1
fref
(12.5-30 MHz)
fref
(12.5-30 MHz)
fref 2
÷ 3
(8.33-20 MHz)
VCO
÷ 24(3)
8.33–20
0
1
fref 3
(25-60 MHz)
fref 3
(25-60 MHz)
fref
(8.33-20 MHz)
0
1
fref 3
(25-60 MHz)
fref 3
÷ 2 (12.5-30 MHz) fref
(8.33-20 MHz)
1
0
1
fref 3
÷ 2 (12.5-30 MHz) fref 3
(25-60 MHz)
fref
(8.33-20 MHz)
1
fref 3
÷ 2 (12.5-30 MHz) fref 3 ÷ 2 (12.5-30 MHz) fref
(8.33-20 MHz)
1. fref is the input clock reference frequency (CCLK or XTAL).
2. QAx connected to FB_IN and FSELA=1, PWR_DN=1.
3. QCx connected to FB_IN and FSELC=1, PWR_DN=1.