- 您现在的位置：买卖IC网 > PDF目录9010 > MPC9330ACR2 (IDT, Integrated Device Technology Inc)IC PLL CLOCK GENERATOR 32-LQFP PDF资料下载
参数资料
| 型号： | MPC9330ACR2 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/13页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GENERATOR 32-LQFP |
| 标准包装： | 2,000 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:6 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 120MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
MPC9330 REVISION 8 DECEMBER 19, 2012
8
2012 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
APPLICATIONS INFORMATION
Power Supply Filtering
The MPC9330 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if this
noise is seen on the power supply pins. Random noise on the
VCC_PLL power supply impacts the device characteristics, for
instance, I/O jitter. The MPC9330 provides separate power supplies
for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of
the device. The purpose of this design technique is to isolate the
high switching noise digital outputs from the relatively sensitive
internal analog phase-locked loop. In a digital system environment
where it is more difficult to minimize noise on the power supplies, a
second level of isolation may be required. The simple but effective
form of isolation is a power supply filter on the VCC_PLL pin for the
MPC9330. Figure 3 illustrates a typical power supply filter scheme.
The MPC9330 frequency and phase stability is most susceptible to
noise with spectral content in the 100 kHz to 20 MHz range.
Therefore the filter should be designed to target this range. The key
parameter that needs to be met in the final filter design is the DC
voltage drop across the series filter resistor RF. From the data sheet,
the ICC_PLL current (the current sourced through the VCC_PLL pin) is
typically 5 mA (10 mA maximum), assuming that a minimum of
2.985 V must be maintained on the VCC_PLL pin. The resistor RF
shown in Figure 3 should have a resistance of 10–15
to meet the
voltage drop criteria.
Figure 3. VCC_PLL Power Supply Filter
The minimum values for RF and the filter capacitor CF are defined
by the required filter characteristics: the RC filter should provide an
attenuation greater than 40 dB for noise whose spectral content is
above 100 kHz. In the example RC filter shown in Figure 3, the filter
cut-off frequency is around 3-5 kHz, and the noise attenuation at 100
kHz is better than 42 dB.
As the noise frequency crosses the series resonant point of an
individual capacitor, its overall impedance begins to look inductive
and, thus, increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance path to
ground exists for frequencies well above the bandwidth of the PLL.
Although the MPC9330 has several design features to minimize the
susceptibility to power supply noise (isolated power and grounds
and fully differential PLL), there still may be applications in which
overall performance is being degraded due to system power supply
noise. The power supply filter schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.
Driving Transmission Lines
The MPC9330 clock driver was designed to drive high-speed
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user, the output drivers were designed
to exhibit the lowest impedance possible. With an output impedance
of less than 20
the drivers can drive either parallel or series
terminated transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note AN1091.
In most high performance clock networks, point-to-point distribution
of signals is the method of choice. In a point-to-point scheme, either
series terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end of the
line with a 50
resistance to VCC2.
This technique draws a fairly high level of DC current and thus
only a single terminated line can be driven by each output of the
MPC9330 clock driver. For the series terminated case, however,
there is no DC current draw, thus the outputs can drive multiple
series terminated lines. Figure 4 illustrates an output driving a single
series terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC9330 clock driver
is effectively doubled due to its capability to drive multiple lines.
Figure 4. Single versus Dual Transmission Lines
The waveform plots in Figure 4 show the simulation results of an
output driving a single line versus two lines. In both cases, the drive
capability of the MPC9330 output buffer is more than sufficient to
drive 50
transmission lines on the incident edge. Note from the
delay measurements in the simulations, a delta of only 43 ps exists
between the two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9330. The output waveform in
Figure 5 shows a step in the waveform; this step is caused by the
impedance mismatch seen looking into the driver. The parallel
combination of the 36
series resistor plus the output impedance
does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
VCC_PLL
VCC
MPC9330
10 nF
RF = 10 – 15
CF
33...100 nF
RF
VCC
CF = 22 F
14
IN
MPC9330
Output
Buffer
RS = 36
ZO = 50
OutA
14
IN
MPC9330
Output
Buffer
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
相关PDF资料 |
PDF描述 |
|---|---|
| MS3456KT10SL-3S | CONN PLUG 3POS STRAIGHT W/SCKT |
| MS27484T24F35SD | CONN PLUG 128POS STRAIGHT W/SCKT |
| M83723/73R24576 | CONN RCPT 57POS JAM NUT W/SCKT |
| VE-20Y-MY-F3 | CONVERTER MOD DC/DC 3.3V 33W |
| VI-J7Z-MZ-F2 | CONVERTER MOD DC/DC 2V 10W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9330FA | 功能描述:时钟发生器及支持产品 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9330FAR2 | 制造商:Integrated Device Technology Inc 功能描述:MPC9330FAR2 - Tape and Reel |
| MPC9331 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3 V 1:6 LVCMOS PLL Clock Generator |
| MPC9331AC | 功能描述:时钟发生器及支持产品 FSL1-6 LVCMOS/LVPECL LVCMOS PLL Clk Gen RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9331ACR2 | 功能描述:时钟发生器及支持产品 FSL1-6 LVCMOS/LVPECL LVCMOS PLL Clk Gen RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
发布紧急采购，3分钟左右您将得到回复。