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| 型号： | MPC9351FAR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件页数： | 4/10页 |
| 文件大小： | 356K |
| 代理商： | MPC9351FAR2 |
MPC9351
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
109
PIN CONFIGURATION
Pin
I/O
Type
Function
PCLK, PCLK
Input
LVPECL
Differential clock reference
Low voltage positive ECL input
TCLK
Input
LVCMOS
Single ended reference clock signal or test clock
EXT_FB
Input
LVCMOS
Feedback signal input, connect to a QA, QB, QC, QD output
REF_SEL
Input
LVCMOS
Selects input reference clock
FSELA
Input
LVCMOS
Output A divider selection
FSELB
Input
LVCMOS
Output B divider selection
FSELC
Input
LVCMOS
Outputs C divider selection
FSELD
Input
LVCMOS
Outputs D divider selection
OE
Input
LVCMOS
Output enable/disable
QA
Output
LVCMOS
Bank A clock output
QB
Output
LVCMOS
Bank B clock output
QC0, QC1
Output
LVCMOS
Bank C clock outputs
QD0 - QD4
Output
LVCMOS
Bank D clock outputs
VCCA
Supply
VCC
Positive power supply for the PLL
VCC
Supply
VCC
Positive power supply for I/O and core
GND
Supply
Ground
Negative power supply
FUNCTION TABLE
Control
Default
0
1
REF_SEL
0
Selects PCLK as reference clock
Selects TCLK as reference clock
PLL_EN
1
Test mode with PLL disabled. The input clock is
directly routed to the output dividers
PLL enabled. The VCO output is routed to the
output dividers
OE
0
Outputs enabled
Outputs disabled, PLL loop is open
VCO is forced to its minimum frequency
FSELA
0
QA = VCO
÷ 2
QA = VCO
÷ 4
FSELB
0
QB = VCO
÷ 4
QB = VCO
÷ 8
FSELC
0
QC = VCO
÷ 4
QC = VCO
÷ 8
FSELD
0
QD = VCO
÷ 4
QD = VCO
÷ 8
ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
Supply Voltage
-0.3
4.6
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
VOUT
DC Output Voltage
-0.3
VCC+0.3
V
IIN
DC Input Current
±20
mA
IOUT
DC Output Current
±50
mA
TS
Storage Temperature
-55
150
°C
a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
GENERAL SPECIFICATIONS
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VTT
Output Termination Voltage
VCC B 2
V
MM
ESD (Machine Model)
200
V
HBM
ESD (Human Body Model)
2000
V
LU
Latch–Up
200
mA
CPD
Power Dissipation Capacitance
10
pF
Per output
CIN
4.0
pF
Inputs
2
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9352 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR |
| MPC9352AC | 功能描述:锁相环 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9352ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-11 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9352FA | 功能描述:锁相环 - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9352FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
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