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| 型号： | MPC9352AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN ZD 1:11 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:11 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC9352 REVISION 8 JANUARY 31, 2013
6
2013 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Table 7. DC Characteristics (VCC = 2.5 V ± 5%, TA = –40° to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
–0.3
0.7
V
LVCMOS
VOH
Output High Voltage
1.8
V
IOH = –15 mA(1)
1. The MPC9352 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output.
VOL
Output Low Voltage
0.6
V
IOL = 15mA
ZOUT
Output Impedance
17 – 20
IIN
Input Current
200
A
VIN = VCC or
GND
ICCA
Maximum PLL Supply Current
2.0
5.0
mA
VCCA Pin
ICCQ(2)
2. ICCQ is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open.
Maximum Quiescent Supply Current
1.0
mA
All VCC Pins
Table 8. AC Characteristics (VCC = 2.5 V ± 5%, TA = –40° to 85°C)(1)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input reference frequency in PLL mode(2)
4 feedback
6 feedback
8 feedback
12 feedback
Input reference frequency in PLL bypass mode(3)
50.0
33.3
25.0
16.67
100.0
66.6
50.0
33.3
250.0
MHz
fVCO
VCO lock frequency range(4)
200
400
MHz
fMAX
Output Frequency
2 output(5)
4 output
6 output
8 output
12 output
100
50
33.3
25
16.67
200
100
66.6
50
33.3
MHz
frefDC
Reference Input Duty Cycle
25
75
%
tr, tf
CCLK Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay CCLK to FB_IN
fref > 40 MHz
(static phase offset)
fref < 40 MHz
–50
–200
+150
ps
PLL locked
tsk(O)
Output-to-output Skew(6)
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
200
100
ps
DC
Output duty cycle
47
50
53
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.6 to 1.8 V
tPLZ, HZ
Output Disable Time
8
ns
tPZL, ZH
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitter
output frequencies mixed RMS (1
)
outputs are in any
4 and 6 combination RMS (1 )
all outputs same frequency RMS (1
)
400
250
100
ps
tJIT(PER)
Period Jitter
output frequencies mixed RMS (1
)
outputs are in any
4 and 6 combination RMS (1 )
all outputs same frequency RMS (1
)
200
150
75
ps
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