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| 型号： | MPC93R51FAR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 93R SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件页数： | 4/9页 |
| 文件大小： | 336K |
| 代理商： | MPC93R51FAR2 |
MPC93R51
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
133
DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0° to 70°C)
Sym-
bol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.8
V
LVCMOS
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
250
mV
LVPECL
VCMRa
Common Mode Range
PCLK, PCLK
1.0
VCC-0.6
V
LVPECL
VOH
Output High Voltage
2.4
V
IOH=-24 mAb
VOL
Output Low Voltage
0.55
0.30
V
IOL= 24 mA
IOL= 12 mA
ZOUT
Output Impedance
14 - 17
W
IIN
Input Leakage Current
±200
A
VIN = VCC or GND
ICCA
Maximum PLL Supply Current
3.0
5.0
mA
VCCA Pin
ICCQ
Maximum Quiescent Supply Current
7.0
10
mA
All VCC Pins
a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b. The MPC93R51 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated trans-
mission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0° to 70°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequencyb
÷ 4 feedback
÷ 8 feedback
Static test mode
50
25
0
120
60
300
MHz
PLL_EN = 1
PLL_EN = 0
fVCO
VCO Frequency
200
480
MHz
fMAX
Maximum Output Frequencyb
÷ 2 output
÷ 4 output
÷ 8 output
100
50
25
240
120
60
MHz
frefDC
Reference Input Duty Cycle
25
75
%
VPP
Peak-to-Peak Input Voltage PCLK, PCLK
500
1000
mV
LVPECL
VCMRc
Common Mode Range
PCLK, PCLK
1.2
VCC-0.9
V
LVPECL
tr, tfd
TCLK Input Rise/Fall Time
1.0
ns
0.8 to 2.0V
t()
Propagation Delay (static phase offset)
TCLK to EXT_FB
PCLK to EXT_FB
–50
+25
+150
+325
ps
PLL locked
tsk(o)
Output-to-Output Skew
150
ps
DC
Output Duty Cycle
100 – 240 MHz
50 – 120 MHz
25 – 60 MHz
45
47.5
48.75
50
55
52.5
51.75
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ
Output Disable Time
7.0
ns
tPZL, ZH
Output Enable Time
6.0
ns
BW
PLL closed loop bandwidth
÷ 4 feedback
÷ 8 feedback
3.0 – 9.5
1.2 – 2.1
MHz
–3 db point of
PLL transfer
characteristic
tJIT(CC)
Cycle-to-cycle jitter
÷ 4 feedback
Single Output Frequency Configuration
10
22
ps
RMS value
tJIT(PER)
Period Jitter
÷ 4 feedback
Single Output Frequency Configuration
8.0
15
ps
RMS value
tJIT()
I/O Phase Jitter
4.0 – 17
ps
RMS value
tLOCK
Maximum PLL Lock Time
1.0
ms
a. AC characteristics apply for parallel output termination of 50
to VTT
b. The PLL will be unstable with a divide by 2 feedback ratio.
c. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
d. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), can only be guaranteed if tr/tf
are within the specified range.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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