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| 型号： | MPC9658AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 1:10 3.3V 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVPECL |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:10 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 250MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC9658 REVISION 6 JANUARY 8, 2013
3
2013 Integrated Device Technology, Inc.
MPC9658 Data Sheet
3.3V 1:10 LVCMOS PLL CLOCK GENERATOR
Table 1. Pin Configurations
Number
Name
Type
Description
PCLK, PCLK
Input
LVPECL
PECL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to QFB
VCO_SEL
Input
LVCMOS
Operating frequency range select
BYPASS
Input
LVCMOS
PLL and output divider bypass select
PLL_EN
Input
LVCMOS
PLL enable/disable
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
Q0–9
Output
LVCMOS
Clock outputs
QFB
Output
LVCMOS
Clock output for PLL feedback, connect to FB_IN
GND
Supply
Ground
Negative power supply (GND)
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external
INFORMATION for details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive
power supply for correct operation.
Table 2. Function Table
Control
Default
0
1
PLL_EN
1
Test mode with PLL bypassed. The reference clock
(PCLK) is substituted for the internal VCO output.
MPC9658 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not
applicable.
Selects the VCO output.(1)
1. PLL operation requires BYPASS = 1 and PLL_EN = 1.
BYPASS
1
Test mode with PLL and output dividers bypassed. The
reference clock (PCLK) is directly routed to the outputs.
MPC9658 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not
applicable.
Selects the output dividers.
VCO_SEL
1
VCO
1 (High frequency range). fREF = fQ0–9 = 2 fVCO
VCO
2 (Low output range). fREF = fQ0–9 = 4 fVCO
MR/OE
0
Outputs enabled (active)
Outputs disabled (high-impedance state) and reset of the
device. During reset the PLL feedback loop is open. The
VCO is tied to its lowest frequency. The length of the reset
pulse should be greater than one reference clock cycle
(PCLK).
Table 3. Absolute Maximum Ratings(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
Supply Voltage
–0.3
3.9
V
VIN
DC Input Voltage
–0.3
VCC +0.3
V
VOUT
DC Output Voltage
–0.3
VCC +0.3
V
IIN
DC Input Current
20
mA
IOUT
DC Output Current
50
mA
TS
Storage Temperature
–65
125
°C
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