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参数资料
| 型号： | MPC9772AE |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/17页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 1:12 3.3V 52-LQFP |
| 标准包装： | 160 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:12 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-LQFP |
| 供应商设备封装： | 52-TQFP（10x10） |
| 包装： | 托盘 |
DATASHEET
3.3V 1:12 LVCMOS PLL Clock Generator
MPC9772
NRND
MPC9772 REVISION 7 JANUARY 8, 2013
1
2013 Integrated Device Technology, Inc.
The MPC9772 is a 3.3 V compatible, 1:12 PLL based clock generator targeted
for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With output
frequencies up to 240 MHz and output skews less than 250 ps the device meets
the needs of the most demanding clock applications.
Features
1:12 PLL Based Low-Voltage Clock Generator
3.3 V Power Supply
Internal Power-On Reset
Generates Cock Signals Up to 240 MHz
Maximum Output Skew of 250 ps
On-Chip Crystal Oscillator Clock Reference
Two LVCMOS PLL Reference Clock Inputs
External PLL Feedback Supports Zero-Delay Capability
Various Feedback and Output Dividers (See Applications Information
Section)
Supports Up to Three Individual Generated Output Clock Frequencies
Synchronous Output Clock Stop Circuitry for Each Individual Output for
Power Down Support
Drives Up to 24 Clock Lines
Ambient Temperature Range 0
C to +70C
Pin and Function Compatible To the MPC972
52-Lead Pb-Free Package
NRND – Not Recommend for New Designs
Use replacement part ICS87972DYI-147
Functional Description
The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as
well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1, and 8:3.
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-
tion the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-
binary factor. The MPC9772 also supports the 180
phase shift of one of its output banks with respect to the other output banks.
The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of sys-
tem baseline timing signals.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL char-
acteristics do not apply.
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
MPC9772. The MPC9772 has an internal power-on reset.
The MPC9772 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission
lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package.
3.3 V 1:12 LVCMOS
PLL CLOCK GENERATOR
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 848D-03
MPC9772
NRND – Not Recommend for New Designs
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9772AER2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9772FA | 功能描述:锁相环 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9772FAR2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9773 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:3.3 V 1:12 LVCMOS PLL Clock Generator |
| MPC9773AE | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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