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| 型号： | MPC9772AE |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 16/17页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 1:12 3.3V 52-LQFP |
| 标准包装： | 160 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:12 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-LQFP |
| 供应商设备封装： | 52-TQFP（10x10） |
| 包装： | 托盘 |
MPC9772 REVISION 7 JANUARY 8, 2013
8
2013 Integrated Device Technology, Inc.
MPC9772 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
APPLICATIONS INFORMATION
MPC9772 Configurations
Configuring the MPC9772 amounts to properly configuring
the internal dividers to produce the desired output
frequencies. The output frequency can be represented by
this formula:
where fREF is the reference frequency of the selected input
clock source (CCLKO, CCLK1 or XTAL interface), M is the
PLL feedback divider and N is a output divider. The PLL
feedback divider is configured by the FSEL_FB[2:0] and the
output dividers are individually configured for each output
bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0]
inputs.
The reference frequency fREF and the selection of the
feedback-divider M is limited by the specified VCO frequency
range. fREF and M must be configured to match the VCO
frequency range of 200 to 480 MHz in order to achieve stable
PLL operation:
fVCO,MIN (fREF VCO_SEL M) fVCO,MAX
The PLL post-divider VCO_SEL is either a divide-by-one
or a divide-by-two and can be used to situate the VCO into
the specified frequency range. This divider is controlled by
the VCO_SEL pin. VCO_SEL effectively extends the usable
input frequency range while it has no effect on the output to
reference frequency ratio.
The output frequency for each bank can be derived from
the VCO frequency and output divider:
fQA[0:3] = fVCO (VCO_SEL NA)
fQB[0:3] = fVCO (VCO_SEL NB)
fQC[0:3] = fVCO (VCO_SEL NC)
Table 11 shows the various PLL feedback and output
configurations for the MPC9772:
VCO_SEL
M
N
fREF
fOUT
fOUT = fREF M N
PLL
Table 11. MPC9772 Divider
Divider
Function
VCO_SEL
Values
M
PLL feedback
FSEL_FB[0:3]
1
4, 6, 8, 10, 12, 16
2
8, 12, 16, 20, 24, 32, 40
NA
Bank A Output
Divider
FSEL_A[0:1]
1
4, 6, 8, 12
2
8, 12, 16, 24
NB
Bank B Output
Divider
FSEL_B[0:1]
1
4, 6, 8, 10
2
8, 12, 16, 20
NC
Bank C Output
Divider
FSEL_C[0:1]
1
2, 4, 6, 8
2
4, 8, 12, 16
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9772AER2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9772FA | 功能描述:锁相环 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9772FAR2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9773 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:3.3 V 1:12 LVCMOS PLL Clock Generator |
| MPC9773AE | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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