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参数资料
| 型号： | MPC9772FA |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 230 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封装： | LQFP-52 |
| 文件页数： | 14/16页 |
| 文件大小： | 833K |
| 代理商： | MPC9772FA |
IDT / ICS 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
7
MPC9772 REV 6 FEBRUARY 7, 2007
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
t()
Propagation Delay (static phase offset)(7)
CCLK to FB_IN
6.25 MHz < fREF < 65.0 MHz
65.0 MHz < fREF < 125 MHz
fREF=50 MHz and feedback=÷8
–3
–4
–166
+3
+4
+166
°
ps
PLL locked
tSK(O)
Output-to-output Skew(8)
within QA outputs
within QB outputs
within QC outputs
all outputs
100
250
ps
DC
Output Duty Cycle(9)
(T
÷2) – 200
T
÷ 2
(T
÷2) + 200
ps
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
8
ns
tPZL, LZ
Output Enable Time
8
ns
tJIT(CC)
Cycle-to-cycle Jitter(10)
150
200
ps
tJIT(PER) Period Jitter(11)
150
ps
tJIT()
I/O Phase Jitter RMS (1
σ)(12)
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
11
86
13
88
16
19
21
22
27
30
ps
(VCO=400 MHz)
BW
PLL closed loop bandwidth(13)
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
1.20 – 3.50
0.70 – 2.50
0.50 – 1.80
0.45 – 1.20
0.30 – 1.00
0.25 – 0.70
0.20 – 0.55
0.17 – 0.40
0.12 – 0.30
0.11 – 0.28
MHz
tLOCK
Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50
to VTT.
2. In bypass mode, the MPC9772 divides the input reference clock.
3. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF= fVCO ÷ (M VCO_SEL).
4. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio:
fXTAL(min, max) = fVCO(min, max) ÷ (M VCO_SEL) and 10 MHz ≤ fXTAL ≤ 25 MHz.
5. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF, MIN.
6. The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(), tPW,MIN, DC and fMAX can only
be guaranteed if tR, tF are within the specified range.
7. Static phase offset depends on the reference frequency. t() [s] = t() [°] ÷ (fREF 360°).
8. Excluding QSYNC output. See application section for part-to-part skew calculation.
9. Output duty cycle is DC = (0.5
± 200 ps fOUT) 100%. E.g. the DC range at fOUT = 100 MHz is 48% < DC < 52%. T = output period.
10. Cycle jitter is valid for all outputs in the same divider configuration. See Applications Information section for more details.
11. Period jitter is valid for all outputs in the same divider configuration. See Applications Information section for more details.
12. I/O jitter is valid for a VCO frequency of 400 MHz. See Applications Information section for I/O jitter vs. VCO frequency.
13. –3 dB point of PLL transfer characteristics.
Table 10. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to +85°C)(1), (2), continued on next page
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
TA = 0°C
to +70°C
TA = –40°C
to +85°C
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9772FAR2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9773 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:3.3 V 1:12 LVCMOS PLL Clock Generator |
| MPC9773AE | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9773AER2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9773FA | 功能描述:锁相环 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
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