- 您现在的位置：买卖IC网 > PDF目录29137 > MPC97H74FAR2 (FREESCALE SEMICONDUCTOR INC) 97H SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 PDF资料下载
参数资料
| 型号： | MPC97H74FAR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 97H SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | LQFP-52 |
| 文件页数： | 8/12页 |
| 文件大小： | 240K |
| 代理商： | MPC97H74FAR2 |
Advanced Clock Driver Devices
Freescale Semiconductor
5
MPC97H74
Table 8. PLL Frequency Ranges (VCC = 3.3 V ± 5%)
Symbol
Characteristics
TA = -40°C to +85°C
TA = 0°C to +70°C
Unit
Condition
Min
Max
Min
Max
fVCO
VCO Frequency Lock Range(1)
1. The input reference frequency must match the VCO frequency lock range divided by the total feedback divider ratio (FB): fREF = fVCO ÷ (M
× VCO_SEL).
210
450
200
500
MHz
fREF
Input Reference Frequency Range
÷ 8 feedback
÷ 12 feedback
÷ 16 feedback
÷ 24 feedback
÷ 32 feedback
÷ 48 feedback
Input Reference Frequency Range in PLL Bypass Mode(2)
2. In bypass mode, the MPC97H74 divides the input reference clock.
26.250
17.500
13.125
8.750
6.5625
4.375
0
56.250
37.500
28.125
18.750
14.0625
9.375
250
25.0
16.6
12.5
8.33
6.25
4.16
0
62.50
41.60
31.25
20.83
15.625
10.41
250
MHz
PLL locked
PLL bypass
fMAX
Output Frequency Range
÷ 4 output
÷ 8 output
÷ 12 output
÷ 16 output
÷ 24 output
52.500
26.250
17.500
13.125
8.750
112.500
56.250
37.500
28.125
18.750
50.00
25.00
16.60
12.50
8.33
125.0
62.50
41.60
31.25
20.83
MHz
PLL locked
Table 9. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = -40°C to +85°C)
(1)
1. AC characteristics apply for parallel output termination of 50
to V
TT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
tPW,MIN
Input Reference Pulse Width(2)
2. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN × fREF × 100% and DCREF,MAX = 100% – DCREF, MIN. E.g. at fREF =62.5 MHz
the input duty cycle range is 12.5% < DC < 87.5%.
2.0
ns
tR, tF
CCLKx Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay (static phase offset)(3)
CCLKx to FB_IN (FB =
÷ 8 and f
REF = 50 MHz)
3. Static phase offset depends on the reference frequency: t() = +50 ps ± (1 ÷ (120 × fREF)) for any reference frequency.
–250
+100
ps
PLL locked
tSK(O)
Output-to-output Skew(4)
within QA bank
within QB bank
within QC bank
any output
4. Refer to Application section for part-to-part skew calculation.
100
125
100
175
ps
DC
Output Duty Cycle
47
50
53
%
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
10
ns
tPZL
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle Jitter(5)
5. Valid for all outputs at the same fequency.
90
ps
tJIT(PER)
Period Jitter(4)
90
ps
tJIT()
I/O Phase Jitter RMS (1
σ)(6)
FB =
÷ 8
FB =
÷ 12
FB =
÷ 16
FB =
÷ 24
FB =
÷ 32
FB =
÷ 48
6. I/O jitter for fVCO = 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter at other frequencies and for a jitter calculation for
confidence factors other than 1
σ.
15
49
18
22
26
34
ps
BW
PLL Closed Loop Bandwidth(7)
FB =
÷ 8
FB =
÷ 12
FB =
÷ 16
FB =
÷ 24
FB =
÷ 32
FB =
÷ 48
7. –3 dB point of PLL transfer characteristics.
0.50 - 1.80
0.30 - 1.00
0.25 - 0.70
0.17 - 0.40
0.12 - 0.30
0.07 - 0.20
MHz
MHZ
MHz
tLOCK
Maximum PLL Lock Time
10
ms
相关PDF资料 |
PDF描述 |
|---|---|
| MPC97H74FA | 97H SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9893FAR2 | 9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| MPC991FAR2 | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC991FAR2 | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC993FA | 993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC980 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:DUAL 3.3V PLL CLOCK GENERATOR |
| MPC9817 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers |
| MPC9817EN | 功能描述:时钟发生器及支持产品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9817ENR2 | 功能描述:时钟发生器及支持产品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9817SD | 功能描述:时钟发生器及支持产品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
发布紧急采购，3分钟左右您将得到回复。