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| 型号： | MPC9893AE |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/14页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 1:12 3.3V 48-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
MPC9893 REVISION 8 JANUARY 16, 2013
7
2013 Integrated Device Technology, Inc.
MPC9893 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
APPLICATIONS INFORMATION
Definitions
IDCS: Intelligent Dynamic Clock Switch. The IDCS monitors
both primary and secondary clock signals. Upon a failure of
the primary clock signal, the IDCS switches to a valid
secondary clock signal and status flags are set.
Reference clock signal fref: The clock signal that is selected
by the IDCS or REF_SEL as the input reference to the PLL.
Manual mode: The reference clock frequency is selected by
REF_SEL.
Automatic mode: The reference clock frequency is
determined by the internal IDCS logic.
Primary clock: The input clock signal selected by REF_SEL.
The primary clock may or may not be the reference clock,
depending on switch mode and IDCS status.
Secondary clock: The input clock signal not selected by
REF_SEL
Selected clock: The CLK_IND flag indicates the reference
clock signal: CLK_IND = 0 indicates CLK0 is the clock
reference signal, CLK_IND =1 indicates CLK1 is the
reference clock signal.
Clock failure: A valid clock signal that is stuck (high or low) for
at least one input clock period. The primary clock and the
secondary clock is monitored for failure. Valid clock signals
must be within the AC and DC specification for the input
reference clock. A loss of clock is detected if as well as the
loss of both clocks. In the case of both clocks lost, the
MPC9893 will set the alarm flags and the PLL will stall. The
MPC9893 does not monitor and detect changes in the input
frequency.
Automatic Mode and IDCS Commanded Clock Switch
MAN/A = 1, IDCS enabled: Both primary and secondary
clocks are monitored. The first clock failure is reported by its
ALARMx status flag (clock failure is indicated by a logic low).
The ALARMx status is flag latched and remains latched until
reset by assertion of ALARM_RST.
If the clock failure occurs on the primary clock, the IDCS
attempts to switch to the secondary clock. The secondary
clock signal needs to be valid for a successful switch. Upon a
successful switch, CLK_IND indicates the reference clock,
which may now be different as that originally selected by
REF_SEL.
Manual Mode
MAN/A = 0, IDCS disabled: PLL functions normally and
both clocks are monitored. The reference clock signal will
always be the clock signal selected by REF_SEL and will be
indicated by CLK_IND.
Clock Output Transition
A clock switch, either in automatic or manual mode,
follows the next negative edge of the newly selected
reference clock signal. The feedback and newly selected
reference clock edge will start to slew to alignment at the next
positive edge of both signals. Output runt pulses are
eliminated.
Reset
ALARM_RST is asserted by a negative edge. It generates
a one-shot reset pulse that clears both ALARMx latches and
the CLK_IND latch. If both CLK0 and CLK1 are invalid or fail
when ALARM_RST is asserted, both ALARMx flags will be
latched after one FB signal period and CLK_IND will be
latched (L) indicating CLK0 is the reference signal. While
neither ALARMx flag is latched (ALARMx = H), the CLK_IND
can be freely changed with REF_SEL.
OE/MR: Reset the data generator and output disable.
Does not reset the IDCS flags.
Acquiring Frequency Lock at Startup
1.
On startup, OE/MR must be asserted to reset the output
dividers. The IDCS should be disabled (MAN/A=0)
during startup to select the manual mode and the
primary clock.
2.
The PLL will attempt to gain lock if the primary clock is
present on startup. PLL lock requires the specified lock
time.
3.
Applying a high to low transition to ALARM_RST will
clear the alarm flags.
4.
Enable the IDCS (MAN/A=1) to enable to IDCS.
Power Supply Filtering
The MPC9893 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCC_PLL (PLL) power supply impacts the device
characteristics, for instance I/O jitter. The MPC9893 provides
separate power supplies for the output buffers (VCC) and the
phase-locked loop (VCC_PLL) of the device. The purpose of
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
power supply filter scheme. The MPC9893 frequency and
phase stability is most susceptible to noise with spectral
content in the 100kHz to 20MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor RF. From the data sheet
the ICC_PLL current (the current sourced through the VCC_PLL
pin) is typically 2 mA (5 mA maximum), assuming that a
minimum of 2.325 V (VCC = 3.3 V or VCC = 2.5 V) must be
maintained on the VCC_PLL pin. The resistor RF shown in
Figure 3 must have a resistance of 9-10
to meet the voltage
drop criteria.
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