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参数资料
| 型号： | MPC9952FA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | PLASTIC, LQFP-32 |
| 文件页数： | 4/5页 |
| 文件大小： | 96K |
| 代理商： | MPC9952FA |
MPC9952
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
285
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tr, tf
Output Rise/Fall Time (Note 4.)
0.10
1.0
ns
0.8 to 2.0V
tpw
Output Pulse Width (Note 4.)
tCYCLE/2
–750
tCYCLE/2
±500
tCYCLE/2
+750
ps
tos
Output-to-Output Skew
Excluding Qa0
(Note 4.)
All Outputs
350
450
550
ps
Same Frequencies
Different Frequencies
fVCO
PLL VCO Lock Range
200
480
MHz
Note 6.
fmax
Maximum Output Frequency
Qc,Qb (
÷2)
Qa,Qb,Qc (
÷4)
Qa (
÷6)
180
120
80
MHz
Note 4.
tpd
REFCLK to FBIN Delay
–200
0
200
ps
Notes 4., 5.
tPLZ, tPHZ
Output Disable Time
2
8
ns
Note 4.
tPZL, tPLH
Output Enable Time
2
10
ns
Note 4.
tjit(cc)
Cycle–to–Cycle Jitter
±100
ps
tlock
Maximum PLL Lock Time
10
ms
4. Termination of 50
to VCCO/2.
5. tpd is specified for 50MHz input ref, the window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods.
The tpd does not include jitter.
6. The PLL may be unstable with a divide by 2 feedback ratio.
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC9952 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of approximately 7
the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
application note AN1091.
Figure 3. Single versus Dual Transmission Lines
7
IN
MPC9952
OUTPUT
BUFFER
RS = 43
ZO = 50
OutA
7
IN
MPC9952
OUTPUT
BUFFER
RS = 43
ZO = 50
OutB0
RS = 43
ZO = 50
OutB1
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a point–to–
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique termi-
nates the signal at the end of the line with a 50
resistance to
VCCO/2. This technique draws a fairly high level of DC current
and thus only a single terminated line can be driven by each
output of the MPC9952 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 3 illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the fan-
out of the MPC9952 clock driver is effectively doubled due to
its capability to drive multiple lines.
The waveform plots of Figure 4 show the simulation results
of an output driving a single line vs two lines. In both cases the
drive capability of the MPC9952 output buffers is more than
sufficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output–to–output skew of the
MPC9952. The output waveform in Figure 4 shows a step in
the waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
43
series resistor plus the output impedance does not match
the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
VL = VS (Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.8V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
2
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相关代理商/技术参数 |
参数描述 |
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| MPC9992 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
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| MPC9992ACR2 | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9992FA | 功能描述:锁相环 - PLL 2.5 3.3V 400MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
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