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参数资料
| 型号： | MPC9990FAR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封装： | PLASTIC, LQFP-48 |
| 文件页数： | 5/10页 |
| 文件大小： | 203K |
| 代理商： | MPC9990FAR2 |
MPC9990
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
290
Table 3: Output Frequency Relationship for an Example Configuration
ASEL[0]
ASEL[1]
BSEL
f QAn
f QBn
f QFB
QSYNC
0
CLK
L
0
1
0
CLK
B 2
CLK
B 2
CLK
enabled
1
0
CLK x 3
B 4
CLK x 3
B 4
CLK
enabled
1
0
CLK x 4
B 5
CLK x 4
B 5
CLK
enabled
0
1
CLK
L
0
1
CLK
B 2
CLK
enabled
1
0
1
CLK x 3
B 4
CLK
enabled
1
CLK x 4
B 5
CLK
enabled
Table 4: Function Table (Controls)
Control Pin
0
1
TEST
PLL enabled
PLL bypassed (Static test mode)
MR
Reset (Internal logic and PLL)
Normal operation mode
OE
Outputs disabled (QX = L, QX = H),
except QFB, QFB
Outputs enabled
VCO_SEL
High frequency operation (VCO
frequency range from 600 to 1150 MHz)
Low frequency operation (VCO
frequency range from 300 to 575 MHz)
Figure 4. QSYNC Phase Relation Diagram
QAx
QFB
QSYNC
The MPC9990 QSYNC output is designed for system syn-
chronization purpose. The output frequency relationship be-
tween the QA–bank and the QFB–output (see table 3) controls
the status of QSYNC. The internal QSYNC pulse circuitry is
enabled if the frequency relationship between the QA–banks
and QFB is not an integer multiple of each other (fQA:fQFB =
1:2, 3:4 and 4:5) (see table 3). QSYNC is asserted (logic high
pulse) centered on coincident rising edges at the QA–bank
outputs and QFB. The QSYNC output transitions at the falling
edges of QFB (assertion at the last falling edge of QFB prior to
the coincident edge event, deassertion at the next falling edge
of QFB). The QSYNC output pulse width is equal to period of
the QFB output (see figure 4, also see the max. skew specifi-
cation QFB to QSYNC).
If BSEL=1 and the PLL is frequency and phase locked,
QSYNC output pulses occur centered on coincident edges be-
tween the QA–bank and QB–bank outputs (offset by the feed-
back path delay) due to the fixed relationship between CLK,
QFB and QB bank outputs.
Table 5: ABSOLUTE MAXIMUM RATINGS*
Symbol
Characteristics
Min
Max
Units
Condition
VCCA
Analog power supply
–0.5
3.6
V
VCC
Core power supply
–0.5
3.6
V
VCCO
Output power supply
–0.5
3.6
V
VIN
Input voltage
–0.5
VCC + 0.3
V
IIN
Input current
–1.0
1.0
mA
DC
IOUT
Output current
–50
50
mA
DC
TS
Storage temperature
–50
150
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or condi-
tions beyond those indicated may adversely affect device reliability. Functional operation at absolute–maximum–rated conditions is not implied.
2
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